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Majority Logic Pre-Sort Decoder

IP.com Disclosure Number: IPCOM000059716D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Kiley, DB: AUTHOR [+2]

Abstract

A decoder or distribution network is used to select one of 2n outputs in response to n inputs. The decoder uses only true inputs and includes two levels of logic. This majority logic pre-sort approach reduces wiring density required of single polysilicon and single metal wiring level circuit designs. The first logic level consists of one or more circuits which provide an output for different combinations of input signals. For example, circuits are used to identify combinations of inputs where all but one are zero, or all but one are one. As the number of inputs increases, additional logic is required to identify combinations of inputs having 2 or more one levels or 2 or more zero levels.

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Majority Logic Pre-Sort Decoder

A decoder or distribution network is used to select one of 2n outputs in response to n inputs. The decoder uses only true inputs and includes two levels of logic. This majority logic pre-sort approach reduces wiring density required of single polysilicon and single metal wiring level circuit designs. The first logic level consists of one or more circuits which provide an output for different combinations of input signals. For example, circuits are used to identify combinations of inputs where all but one are zero, or all but one are one. As the number of inputs increases, additional logic is required to identify combinations of inputs having 2 or more one levels or 2 or more zero levels. The second logic stage includes additional logic, primarily simple NOR or NAND gates, responsive to one or more of the inputs and the output of the first logic stage. Second-stage logic NAND gates require an inverting buffer to generate the proper output level. The second logic circuits include one n-input NOR gate, or equivalent, for all the "ones" input, n 2-input NORs, n 2-input NANDs, with the remainder of the 2n gates being equally divided between 3, or more, input NAND and NOR gates. As an example, a 3 by 8 decoder is diagrammed wherein one pre-sort circuit is employed which replaces the 3 true-complement circuits normally required.

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