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Selective Deposition of Studs to Interconnect Metallization Layers Separated by an Insulator

IP.com Disclosure Number: IPCOM000059718D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Bertelsen, B: AUTHOR [+2]

Abstract

A self-aligned three-dimensional wiring process is described which improves the contact resistance, results in a higher conductive line pitch and significantly simplifies the process of via stud formation. After a via is created in an insulator, the via is partially filled by a selective deposition of tungsten. A layer of aluminum (Al) is then selectively deposited in the via on top of the tungsten (W). A layer of tungsten or molybdenum (Mo) is then selectively deposited over the aluminum layer. Layers of titanium (Ti) and aluminum are then non- selectively deposited over the entire surface and are etched using conventional reactive ion etch (RIE) techniques. The "selective" depositions of the above metals are accomplished by adjusting the chemical vapor deposition (CVD) parameters, such as gas type, pressure and temperature.

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Selective Deposition of Studs to Interconnect Metallization Layers Separated by an Insulator

A self-aligned three-dimensional wiring process is described which improves the contact resistance, results in a higher conductive line pitch and significantly simplifies the process of via stud formation. After a via is created in an insulator, the via is partially filled by a selective deposition of tungsten. A layer of aluminum (Al) is then selectively deposited in the via on top of the tungsten (W). A layer of tungsten or molybdenum (Mo) is then selectively deposited over the aluminum layer. Layers of titanium (Ti) and aluminum are then non- selectively deposited over the entire surface and are etched using conventional reactive ion etch (RIE) techniques. The "selective" depositions of the above metals are accomplished by adjusting the chemical vapor deposition (CVD) parameters, such as gas type, pressure and temperature. These adjustments cause the metals to selectively deposit on other metals and/or the semiconductor substrate without depositing on the insulating layer. PROCESS 1) Formation of vias in an insulator layer. 2) Formation of the via structure. a) Selective CVD of a tungsten (W) diffusion barrier layer at thickness < 100 nm. Since the via exposes a portion of the silicon substrate, the tungsten will only be deposited within the via. b) Selective CVD of Al/Si (Z 0.2% Si) alloy which serves as the major conductor. Thickness equals the depth of the shallowes...