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Address Compare Circuit

IP.com Disclosure Number: IPCOM000059720D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Penoyer, RF: AUTHOR

Abstract

By means of the complementary metal oxide semiconductor (CMOS) circuit shown in the figure, "compare" requirements for hierarchy memory addressing is satisfied with a minimum number of devices and with high performance. If addresses A1, A2, ..., An are equal to addresses B1, B2, ..., Bn, then output remains high. If the addresses are unequal, output is pulled low. A clock device C may be included in the ground connection to avoid problems with address timing skews. Note that load device L may be either a resistor, a depletion device, or other suitable element. All transistors in the circuit not marked P (P-channel) are N-channel devices. If desired, the circuit may be modified to use all N channel transistors.

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Address Compare Circuit

By means of the complementary metal oxide semiconductor (CMOS) circuit shown in the figure, "compare" requirements for hierarchy memory addressing is satisfied with a minimum number of devices and with high performance. If addresses A1, A2, ..., An are equal to addresses B1, B2, ..., Bn, then output remains high. If the addresses are unequal, output is pulled low. A clock device C may be included in the ground connection to avoid problems with address timing skews. Note that load device L may be either a resistor, a depletion device, or other suitable element. All transistors in the circuit not marked P (P- channel) are N-channel devices. If desired, the circuit may be modified to use all N channel transistors. In this modification, the combination of an N channel device driven by an inverter is substituted for each P channel device. Furthermore, the load device L may be a clocked P channel transistor with the clock device C being an N channel transistor.

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