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Early Restore of Column Address Strobe for Dense Random-Access Memories in Page Mode

IP.com Disclosure Number: IPCOM000059724D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+3]

Abstract

An improved Column Address Strobe (CAS) restore cycle, page cycle and better power distribution in a random-access memory (RAM) is accomplished by allowing several CAS restore phases to proceed while the CAS signal is still active. The CAS precharge time and, consequently, the CAS cycle time in page mode for a dense dynamic random-access memory, is improved by performing some CAS restoring during the open Data Valid Window. The new restore sequence shown in the figure show 1 - 4, then 5, with 6, 7 and 8 in parallel with 5 compared with the conventional sequence 1 - 5 then 6, 7, & 8 in series. The advantages gained include: 1) Improved power distribution because the restore phases occur in a more time-distributed fashion.

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Early Restore of Column Address Strobe for Dense Random-Access Memories in Page Mode

An improved Column Address Strobe (CAS) restore cycle, page cycle and better power distribution in a random-access memory (RAM) is accomplished by allowing several CAS restore phases to proceed while the CAS signal is still active. The CAS precharge time and, consequently, the CAS cycle time in page mode for a dense dynamic random-access memory, is improved by performing some CAS restoring during the open Data Valid Window. The new restore sequence shown in the figure show 1 - 4, then 5, with 6, 7 and 8 in parallel with 5 compared with the conventional sequence 1 - 5 then 6, 7, & 8 in series. The advantages gained include: 1) Improved power distribution because the restore phases occur in a more time-distributed fashion. 2) Better utilization of the Bit Decode Set device (used in RAMs which have multiplexed address register lines) by allowing the Bit Storage Address Register (SAR) Reset, Bit Decode Restore and Data Latch Reset 7 restore to proceed simultaneously without overlapped currents. After Data Latch set time, which begins driving the information out on a Read, there is no need for the CAS Start, Bit SAR Drive and Decode or the Bit Switch Drive phases to remain high since these functions have already served their purpose. Similarly on a Write, the array is sufficiently over-written by Data Latch set time that the same restore may occur. Therefore, on a Read or Write, the r...