Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Test Method for Internal Tristate Drivers

IP.com Disclosure Number: IPCOM000059727D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Dittus, B: AUTHOR [+4]

Abstract

A test method is described which permits testing the high impedance state of chip-internal tristate drivers that are not accessible from the outside. The figure shows four tristate drivers TSD1 to TSD4, connected to associated receivers REC1 to REC4 through a bus, and the first test step. The bus is used as a dynamic storage element. The high impedance state of the tristate drivers is tested relative to the information stored on the bus. If the high impedance state has been reached, the stored information will be retained, whereas otherwise it will be altered. The receiving circuits are used to read information from the bus. Testing proceeds as follows: 1. - TSD1, TSD2, TSD3 are tested. - TSD1, TSD2, TSD3 are in the high impedance state, the data stored being "1". - TSD4 writes a "0" onto the bus.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 95% of the total text.

Page 1 of 2

Test Method for Internal Tristate Drivers

A test method is described which permits testing the high impedance state of chip-internal tristate drivers that are not accessible from the outside. The figure shows four tristate drivers TSD1 to TSD4, connected to associated receivers REC1 to REC4 through a bus, and the first test step. The bus is used as a dynamic storage element. The high impedance state of the tristate drivers is tested relative to the information stored on the bus. If the high impedance state has been reached, the stored information will be retained, whereas otherwise it will be altered. The receiving circuits are used to read information from the bus. Testing proceeds as follows: 1. - TSD1, TSD2, TSD3 are tested. - TSD1, TSD2, TSD3 are in the high impedance state, the data stored being "1". - TSD4 writes a "0" onto the bus. - TSD4 also assumes the high impedance state. - In the absence of the high impedance state for TSD1, TSD2 or TSD3, the bus is switched to "1". 2. - The test is repeated with opposite data. 3. - TSD4 is tested in the same manner. As previously mentioned, the proposed test method permits testing the high impedance state of tristate drivers, without the driver outputs having to be accessible from the outside, which is a prerequisite for known off-chip driver tests. The test method described may be used for bipolar and FET technologies, VLSI/GSI (very large-scale integration/grand-scale integration) chips and all logic and microproc...