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Merged Bipolar-Cmos Device

IP.com Disclosure Number: IPCOM000059734D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Sunaga, T: AUTHOR

Abstract

A new merged bipolar (BI)-CMOS device structure in which the base and the drain share the same diffusion area is proposed. Base currents are supplied by high input impedance MOSFETs, making possible bipolar complementary pair. The area efficient device realizes both a low power dissipation comparable to CMOS and a high current-handling capability of bipolar transistors There are two technologies in silicon logic devices: MOSFETs and bipolar transistors. Because of its low power dissipation, a CMOS device is suitable for high density circuits. It, however, has a poor current-handling capability. The propagation delay degrades severely when it drives a large load capacitance. On the other hand, a bipolar transistor has an excellent current-handling capability. It has been widely accepted in high speed applications.

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Merged Bipolar-Cmos Device

A new merged bipolar (BI)-CMOS device structure in which the base and the drain share the same diffusion area is proposed. Base currents are supplied by high input impedance MOSFETs, making possible bipolar complementary pair. The area efficient device realizes both a low power dissipation comparable to CMOS and a high current-handling capability of bipolar transistors There are two technologies in silicon logic devices: MOSFETs and bipolar transistors. Because of its low power dissipation, a CMOS device is suitable for high density circuits.

It, however, has a poor current-handling capability. The propagation delay degrades severely when it drives a large load capacitance. On the other hand, a bipolar transistor has an excellent current-handling capability. It has been widely accepted in high speed applications. But it is difficult to build bipolar VLSI circuits because of its high power dissipation. A low input impedance makes it impossible to realize a CMOS-like complementary pair. Recently a BI-CMOS technology which implements bipolar transistors and CMOS FETs on the same chip has been developed to exploit the advantages of both CMOS and bipolar circuits. Many applications on chip I/O circuits have been reported [*]. In conventional BI-CMOS technologies, bipolar and CMOS circuits are built separately by the same process. Outputs of the individual MOSFETs are connected to bipolar transistors by metal wiring. Then they generally occupy a large area. This invention proposes to build merged bipolar and CMOS circuits in which the base and the drain share the same diffusion rather than separate devices. It realizes an area efficient BI-CMOS logic element. Fig. 1 shows the structure, and its equivalent circuit is shown in Fig. 2. The merged BI-CMOS device shown in Fig. 1 can be fabricated by a conventional N-well CMOS process with two tailored ion implantations for P and N base regions. An NPN transistor consists of an N-well collector 3, a P base 10, and an N+ emitter 11. The optimum intrinsic base 10 is tailored by one of the added ion implantation processes. An extrinsic base 9 and a source region 8 are built simultaneously by a Pion implantation. The P+ source 8, the P+ drain 9, polysilicon gate 7, and channel region 6 make a P MOSFET. When a voltage on the gate 7 decreases below a threshold level, a base current is supplied from the P MOSFET and the NPN transistor 3, 10, 11 turns on. In this connection the reference numbers 4,5,12,13,14,27 and 28 show a field oxide, field stop (P+) region, N+ contact region, AL contact (VDD), AL contact (emitter), inter-layer oxide and gate oxide, respectively. Similarly, PNP transistor regions (l,2), 20, and 21 make a P collector, an N base, and a P+ emitter, respectively. An N MOSFET consists of an N+ drain 19, an N+ source 18, a polysilicon gate 17, and an N channel region
16. When a voltage on the gate 17 increases above a threshold level, the PNP transistor 2, 20,...