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SENSE Amplifier for a Complementary Metal Oxide Silicon Read-Only Memory

IP.com Disclosure Number: IPCOM000059737D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Wissel, L: AUTHOR

Abstract

This circuit performs the sense amplifier function for a complementary metal oxide silicon (CMOS) read-only memory (ROM). By means of a positive feedback, a small signal (just over 1 volt) on a bit line is amplified to about 5 volts. The circuit diagram depicts the sense amplifier, along with two representative bit lines with their restore and bit switch devices. Prior to an access, bit lines are precharged by the signal BLRES to a voltage [Vdd - Vtn]. The bit lines are left floating after access. If a personalized array device exists at the address accessed, it will conduct charge away from the bit line, reducing the bit line voltage.

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SENSE Amplifier for a Complementary Metal Oxide Silicon Read-Only Memory

This circuit performs the sense amplifier function for a complementary metal oxide silicon (CMOS) read-only memory (ROM). By means of a positive feedback, a small signal (just over 1 volt) on a bit line is amplified to about 5 volts. The circuit diagram depicts the sense amplifier, along with two representative bit lines with their restore and bit switch devices. Prior to an access, bit lines are precharged by the signal BLRES to a voltage [Vdd - Vtn]. The bit lines are left floating after access. If a personalized array device exists at the address accessed, it will conduct charge away from the bit line, reducing the bit line voltage. The large capacitance of the bit line, combined with the low current capacity of a read-only store (ROS) array device, limits the discharge of the bit line to a rate that does not quickly develop a large signal. A sense amplifier is needed to amplify the bit line signal soon after discharge begins, improving the access time. The circuit shown performs this function. If, for example, the address selects Bit Line 0, then signal BSW0 will remain high and signal BSW1 will fall when an access is made, thereby passing the signal on Bit Line 0 to the gate of the sense amplifier transistor T2. The signal SENSEN is high during restore, establishing zero voltages on nodes REF and SIG. When a reference word line circuit indicates that word line selection is complete, the signal SENSE rises (and SENSEN falls), pulling node REF to [Vdd - Vtn]*, the same level as that to which the bit line was pre-charged. If an array device is present on the selected bit line, then the gate voltage of transistor T2 falls. As soon as this voltage reaches [Vdd - Vtn - Vtp *], namely Vtp below the bit line pre-charge value, t...