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Bus Size Independent Architecture

IP.com Disclosure Number: IPCOM000059742D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Aoki, Y: AUTHOR [+2]

Abstract

A circuit is described which makes it possible to keep software compatibility when the size of bus between a memory read/write circuit and an image memory is changed. With reference to Fig. 1, a position selector 2 includes four multiplexers 20, 21, 22 and 23, each of which selects one bit from among MPU data bus bits 0, l, 2 and 3 in accordance with a bus size signal and a corresponding memory plane number signal. Selected data bits 0, l, 2 and 3 output from the multiplexers 20, 21, 22 and 23 are provided to memory read/write circuits 30, 31, 32 and 33, respectively. The read/write circuits 30, 31, 32 and 33 include a map mask register, color compare register, a color don't care register, an enable set rest register etc.

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Bus Size Independent Architecture

A circuit is described which makes it possible to keep software compatibility when the size of bus between a memory read/write circuit and an image memory is changed. With reference to Fig. 1, a position selector 2 includes four multiplexers 20, 21, 22 and 23, each of which selects one bit from among MPU data bus bits 0, l, 2 and 3 in accordance with a bus size signal and a corresponding memory plane number signal. Selected data bits 0, l, 2 and 3 output from the multiplexers 20, 21, 22 and 23 are provided to memory read/write circuits 30, 31, 32 and 33, respectively. The read/write circuits 30, 31, 32 and 33 include a map mask register, color compare register, a color don't care register, an enable set rest register etc. The read/write circuits 30, 31, 32 and 33 are connected to image memory planes 0, l, 2 and 3, respectively, via 8-bit buses. In 8-bit mode, the multiplexers 20, 21, 22 and 23 receive the bus size signal showing 8 bits as a first control signal. Further, the multiplexers 20, 21, 22 and 23 receive the corresponding number signals showing 0, l, 2 and 3 as the second control signals, respectively. So, the multiplexers 20, 21, 22 and 23 output the MPU data bits 0, l, 2 and 3 as the selected data bits 0, l, 2 and 3, respectively. In 16-bit mode, the multiplexers 20, 21, 22 and 23 receive the bus size signal showing 16 bits as the first control signal. Further, the multiplexers 20, 21, 22 and 23 receive the corresponding number signals showing 0, 0, 1 and l as the second control signals. So, the multiplexers 20, 21, 22 and 23 output the MPU data bus bits 0, 0, 1 and 1 as the selected data bits 0, l, 2 and 3, respectively. If the read/write circuits 30 and 3...