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Testable Two-Phase Clock Generation Circuit

IP.com Disclosure Number: IPCOM000059745D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Martin, DE: AUTHOR

Abstract

Former solutions contained feed-forward circuits which prevented testing the clock circuit or controlling the clock circuit in an LSSD (level sensitive scan design) test environment. The circuit shown in Fig. 1 generates a two-phase, non-overlapping clock sequence from a single-phase input. The circuit is composed of logic blocks commonly found in LSSD masterslice technologies. Unlike other approaches, the use of a latch in the delay path allows the circuit to meet all LSSD testability groundrules. The A, B, and C clocks may be independently controlled from primary inputs. The two-phase output is generated by having one phase active when the input clock is active, and the second phase active when the input is inactive.

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Testable Two-Phase Clock Generation Circuit

Former solutions contained feed-forward circuits which prevented testing the clock circuit or controlling the clock circuit in an LSSD (level sensitive scan design) test environment. The circuit shown in Fig. 1 generates a two-phase, non-overlapping clock sequence from a single-phase input. The circuit is composed of logic blocks commonly found in LSSD masterslice technologies. Unlike other approaches, the use of a latch in the delay path allows the circuit to meet all LSSD testability groundrules. The A, B, and C clocks may be independently controlled from primary inputs. The two-phase output is generated by having one phase active when the input clock is active, and the second phase active when the input is inactive. Level sensitive master slave latches, such as those found in an LSSD design, require not only two-clock phases, but the clock phases may not overlap. The time between phase one active and phase two active is technology specific, but must always be greater than zero. Fig. 2 is a clock timing description. The non-overlap is provided by delaying the input clock ANDing the input with the delayed version. The delay introduced between the two paths becomes the non- overlap time. LSSD testability groundrules require that the "B" clock be brought to a primary output if it is internally gated. Therefore, the B clock output of the AND gate must go to a primary output, as well as the internal circuitry. During norma...