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Two-Mask Silicon Lift-Off Process to Obtain Self-Aligned Field to N-Well Doping for CMOS

IP.com Disclosure Number: IPCOM000059748D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Furukawa, T: AUTHOR [+3]

Abstract

A process is described using two masking steps for making self-aligned field and N-well doping regions in the manufacture of complementary metal oxide silicon (CMOS) integrated circuits. This process results in improvement in manufacturability over previous silicon lift-off processes used to obtain self-alignment of field to N-well doping regions. The figure represents the structure following the vacuum deposition of silicon (step h of the process description below). Process description begins on P- epitaxial silicon 2, as follows: a. 40 nm of thermal SiO2, pad oxide 4, is grown. b. 100 nm of silicon nitride (Si3N4), pad nitride 6, is deposited by low pressure chemical vapor deposition (LPCVD). c. 150 nm of LPCVD polycrystalline silicon 8 is deposited. d.

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Two-Mask Silicon Lift-Off Process to Obtain Self-Aligned Field to N-Well Doping for CMOS

A process is described using two masking steps for making self-aligned field and N-well doping regions in the manufacture of complementary metal oxide silicon (CMOS) integrated circuits. This process results in improvement in manufacturability over previous silicon lift-off processes used to obtain self- alignment of field to N-well doping regions. The figure represents the structure following the vacuum deposition of silicon (step h of the process description below). Process description begins on P- epitaxial silicon 2, as follows: a. 40 nm of thermal SiO2, pad oxide 4, is grown. b. 100 nm of silicon nitride (Si3N4), pad nitride 6, is deposited by low pressure chemical vapor deposition (LPCVD). c. 150 nm of LPCVD polycrystalline silicon 8 is deposited. d. A photomasking and etching step removes undesired portions of silicon 8 and Si3N4 6, leaving the pads shown. e. After photoresist (not shown) removal, 10 to 30 nm of Si3N4 10 is deposited by LPCVD to act as an etch stop later in the process. f. A photomasking and development step leaves openings in the photoresist 12 which define the N-well regions to be ion implanted. g. Boron ion implantation forms the doped N-well region 16. h. 320 nm of polycrystalline silicon 14 is vacuum deposited. i. Lift-off is performed, removing all of the photoresist 12 and the silicon 14 which was deposited on the photoresist 12. j. N-well drive...