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Settling Clamp Circuit for Digital-To-Analog Converter

IP.com Disclosure Number: IPCOM000059800D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Trnka, JT: AUTHOR [+2]

Abstract

A circuit technique that reduces the time required for a digital-to- analog converter (DAC) to settle to the proper voltage level during a digital-to-analog conversion. The figure shows a partial schematic of a DAC. Devices Qa and Qb form a conventional PNP current mirror. Devices Q1-Qn are PNP current sources that drive the R-2R resistor ladder network depending on the state of the digital inputs BO-Bn. For example, if BO is a 'ONE', transistor Q1 is ON, sourcing current to the R-2R network. If BO is a 'ZERO', transistor Q1 is cut off and does not source current to the ladder network. The worst-case DAC settling time occurs when BO-Bn switch from all 'ONES' to all 'ZEROS'. During this case current mirror Qa and Qb and its associated nodes A and B experience the greatest change in bias conditions.

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Settling Clamp Circuit for Digital-To-Analog Converter

A circuit technique that reduces the time required for a digital-to- analog converter (DAC) to settle to the proper voltage level during a digital-to-analog conversion. The figure shows a partial schematic of a DAC. Devices Qa and Qb form a conventional PNP current mirror. Devices Q1-Qn are PNP current sources that drive the R-2R resistor ladder network depending on the state of the digital inputs BO-Bn. For example, if BO is a 'ONE', transistor Q1 is ON, sourcing current to the R-2R network. If BO is a 'ZERO', transistor Q1 is cut off and does not source current to the ladder network. The worst-case DAC settling time occurs when BO-Bn switch from all 'ONES' to all 'ZEROS'. During this case current mirror Qa and Qb and its associated nodes A and B experience the greatest change in bias conditions. The resulting glitch that occurs at nodes A and B is reflected in the R-2R ladder network via current sources Q1- Qn, increasing the DAC settling time. The DAC settling time is improved by adding a clamping circuit comprised of NPN transistor Qc and bias resistors R1 and Rc. Any negative transition at node A, introduced by BO-Bn switching, will turn on Qc, clamping node A from negative glitches (positive transitions are minimized by Qb) resulting in a fast settling time at the DAC output. Bias resistors R1 and Rc are sized to keep Qc at a low bias level during steady-state conditions.

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