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Logic Partitioning in VLSI Chips to Improve Failure Analysis

IP.com Disclosure Number: IPCOM000059803D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Floyd, R: AUTHOR [+2]

Abstract

A method is described to speed up the failure analysis of chip defects on very large-scale integrated (VLSI) chips by partitioning the logic. The time required to analyze defects on VLSI chips due to the increasing number of devices on a chip can be a problem. One of the physical design concepts that is being employed more and more to make this complexity more manageable is called a macro design concept. Logic is broken up into partitions, such as an ALU, ROS, or an Incrementer. As these macros become larger and larger, the ability to quickly find a defect decreases. In the new technique, all logic macro outputs that would not normally go to a latch when connected to another logic macro are forced to go to a latch. The L1 terminal of the latch would then feed all the places the macro signal was feeding.

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Logic Partitioning in VLSI Chips to Improve Failure Analysis

A method is described to speed up the failure analysis of chip defects on very large-scale integrated (VLSI) chips by partitioning the logic. The time required to analyze defects on VLSI chips due to the increasing number of devices on a chip can be a problem. One of the physical design concepts that is being employed more and more to make this complexity more manageable is called a macro design concept. Logic is broken up into partitions, such as an ALU, ROS, or an Incrementer. As these macros become larger and larger, the ability to quickly find a defect decreases. In the new technique, all logic macro outputs that would not normally go to a latch when connected to another logic macro are forced to go to a latch. The L1 terminal of the latch would then feed all the places the macro signal was feeding. The figure shows how these latches would be added into the logic. The L1 output of the latches would be the new sources for random logic macro (RLM) 1 outputs. Presently, in order to go from one RLM to another, the outputs of RLMs must be buffered. Because of this, the performance impact will not be as great because the L1 latch would take the place of the buffer. A new input called "test clock" is required. During functional operation, "test clock" is always on, allowing the RLM output signals to flush right through the L1 latches. During testing, these latches are part of a scan string. The tester is a...