Browse Prior Art Database

Merging of Different Chips Onto a Single Chip

IP.com Disclosure Number: IPCOM000059805D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Torres, A: AUTHOR

Abstract

A method is described which allows the merging of several chips onto the same chip without having to regenerate the test data or change the logic. This method will allow the use of the original test data generated for the original chips. It also will allow the logic for the two chips to be merged onto a single chip without changing their logic. In order to use the original test data, a tester must be able to observe and apply stimulus to the original primary inputs and outputs of each chip. Fig. 1 shows the interface that occurs on signals in which both chips A and B drive. In this case, a latch with a tristateable output must be fed and must feed the signal driven by both A and B. The latch must also have a scan port that will allow a tester to scan data in whenever the tester wants to drive the signal.

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Merging of Different Chips Onto a Single Chip

A method is described which allows the merging of several chips onto the same chip without having to regenerate the test data or change the logic. This method will allow the use of the original test data generated for the original chips. It also will allow the logic for the two chips to be merged onto a single chip without changing their logic. In order to use the original test data, a tester must be able to observe and apply stimulus to the original primary inputs and outputs of each chip. Fig. 1 shows the interface that occurs on signals in which both chips A and B drive. In this case, a latch with a tristateable output must be fed and must feed the signal driven by both A and B. The latch must also have a scan port that will allow a tester to scan data in whenever the tester wants to drive the signal. When A or B is tested, the macro which is not under test is forced to drive its off-chip drive to the high impedance state. The tester would scan into the isolation latches, the values required to be applied to a signal that originally was a primary input. When a value from chip A or B is to be sampled on the bidirectional output, the isolation latch will latch the output of the Output Chip Driver (OCD). The tester would scan out the values on the isolation latches. A second type of interface between two chips is shown in Fig. 2. Here, one chip's OCD is an output only and drives the second chip. In this case, a latch would be put in the path of the signal with the output of the master latch now feeding the receiver. Durin...