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Two-Speed Receive Method to Prevent Printer Interface Time-Out

IP.com Disclosure Number: IPCOM000059807D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Abbott, RD: AUTHOR

Abstract

A technique is described whereby two-speed interface controls are incorporated between a host computer system and an attachment communications interface so as to prevent a "time-out" interrupt condition. Time-out conditions could cause faulty interruptions in applications requiring extensive operations of attachment devices, such as printers printing high resolution graphics. The two-speed interface control concept provides an inexpensive method of eliminating faulty time-out interrupts by using a circular 1K memory buffer and by regulating the rate of data flow to an attachment device. An algorithm allows data flow to the attachment to proceed at either high speed or low speed by using increment counters to detect and control the data reception rate.

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Two-Speed Receive Method to Prevent Printer Interface Time-Out

A technique is described whereby two-speed interface controls are incorporated between a host computer system and an attachment communications interface so as to prevent a "time-out" interrupt condition. Time-out conditions could cause faulty interruptions in applications requiring extensive operations of attachment devices, such as printers printing high resolution graphics. The two-speed interface control concept provides an inexpensive method of eliminating faulty time-out interrupts by using a circular 1K memory buffer and by regulating the rate of data flow to an attachment device. An algorithm allows data flow to the attachment to proceed at either high speed or low speed by using increment counters to detect and control the data reception rate. When host processor 10, as shown in the figure, places a byte of data or a command on data bus 11 and activates strobe line 12 with a strobe pulse, the strobe pulse loads the data into latch 13 located on the attachment device card and sets flip-flop 14 which posts an interrupt in microprocessor 15. Flip-flop 16 is then set to activate busy line 17 back to host processor 10. The host will not send data to the attachment device while the busy line is activated. Microprocessor 15 then triggers acknowledgement 18 back to host 10. Busy line 17 remains active until the attachment device is ready to receive more data. During the normal reception of data, microprocessor 15 controls the reading and writing of data to receive buffer 19, which is a self- contained encoded representation of the object to be printed by the attachment device. Receive buffer 19 has a capacity of 1024 bytes (1K bytes). Microprocessor 15 contains a write and a read pointer which are respectively incremented as data is written into and removed from receive buffer
19. When either pointer reaches the top of the address range, the pointer will revert back to the bottom of the address range; therefore, a circular buffer is achieved. An algorithm determines if receive buffer 19 is 75 percent full. If receive buffer 19 is less than 75 percent full, then normal reception of data is allowed to...