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Buffer Memory With Detection of Data Errors And Errors Caused by Faults in the Read And Write Address Registers

IP.com Disclosure Number: IPCOM000059831D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Duffy, DM: AUTHOR [+3]

Abstract

A buffer has a storage array and a read address register and a write address register that are independently incremented to address the array as a circular list, as is conventional. The address registers each have low order bit positions that provide the array address and have a next higher order bit position. As the addresses are incremented, the high order bit switches between 0 and 1 on alternate passes through the array.

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Buffer Memory With Detection of Data Errors And Errors Caused by Faults in the Read And Write Address Registers

A buffer has a storage array and a read address register and a write address register that are independently incremented to address the array as a circular list, as is conventional. The address registers each have low order bit positions that provide the array address and have a next higher order bit position. As the addresses are incremented, the high order bit switches between 0 and 1 on alternate passes through the array.

An Exclusive OR circuit for the write addressing circuits receives two bits: the high order bit of the write address register and a control bit from an associated processor. When the control bit is a logical 1, the bit at the output of the Exclusive OR circuit is the complement of the high order bit of the write address counter, and when the control bit is a logical 0 the output is the true value of the high order bit. A similar Exclusive OR circuit is provided in the read addressing circuits.

The array is two bytes wide and is implemented in two separately addressable circuit modules that are each two bytes wide. On a write operation the bit at the output of the write Exclusive OR circuit is stored in one bit position of the addressed location of each module. On a read operation, these are read and are compared with the bit at the output bit of the write Exclusive OR circuit. In normal operation, the output of the read Exclusive OR...