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Loss of Synchronism Detector for Serial Data Detector

IP.com Disclosure Number: IPCOM000059834D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Boerstler, DW: AUTHOR

Abstract

A circuit detects a loss of synchronism between a local clock and transitions in a serial waveform in which data is represented by a transition or the absence of a transition. An Exclusive OR circuit has one input connected to receive the serial waveform directly and a second input connected to receive the serial waveform through a delay circuit. The two inputs have equal binary values except for the time while a transition is propagating through the inverter, and the Exclusive OR circuit produc pulse for each transition. The pulses from the Exclusive OR circuit are transmitted through a non-inverting delay circuit.

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Loss of Synchronism Detector for Serial Data Detector

A circuit detects a loss of synchronism between a local clock and transitions in a serial waveform in which data is represented by a transition or the absence of a transition. An Exclusive OR circuit has one input connected to receive the serial waveform directly and a second input connected to receive the serial waveform through a delay circuit. The two inputs have equal binary values except for the time while a transition is propagating through the inverter, and the Exclusive OR circuit produc pulse for each transition. The pulses from the Exclusive OR circuit are transmitted through a non-inverting delay circuit. The delay circuit introduces a delay of one quarter of the period of a bit time, and if the local clock is synchronized with the transitions, the transition pulse is in the middle of the down half cycle of the local clock. If synchronism is lost, the transition pulse drifts ahead or behind until it falls in the up level of the local clock signal. An AND circuit detects the coincidence of up levels of the transition pulse and the local clock and signals loss of synchronism. The width of the transition pulse controls the amount of phase shift that occurs befo the AND circuit detects loss of synchronism, and the width of this pulse is controlled by the delay at the delayed input of the Exclusive OR circuit.

The drawing shows the serial data line 2, the Exclusive OR circuit 3, the delay 4, the delay ci...