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Clock for Data Processor With Circuit for Adjusting the Clock Frequency

IP.com Disclosure Number: IPCOM000059838D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Smith, GW: AUTHOR

Abstract

The clock of a data processor is commonly made adjustable so that certain tests can be made during manufacturing. In one adjustable clock system, the clock receives a three bit control i that is decoded to select one of eight different frequencies. In the proposed clock circuit, the three original control inputs are adapted to control a counter and the counter value is decoded to control the clock frequency. One of the original control inputs to the circuit increments the counter, one decrements the counter, and one resets the counter to the count for the normal operating frequency. The length of the counter is independent of the number of control inputs and the counter is made large enough to vary the clock frequency over a wide range.

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Clock for Data Processor With Circuit for Adjusting the Clock Frequency

The clock of a data processor is commonly made adjustable so that certain tests can be made during manufacturing. In one adjustable clock system, the clock receives a three bit control i that is decoded to select one of eight different frequencies. In the proposed clock circuit, the three original control inputs are adapted to control a counter and the counter value is decoded to control the clock frequency. One of the original control inputs to the circuit increments the counter, one decrements the counter, and one resets the counter to the count for the normal operating frequency. The length of the counter is independent of the number of control inputs and the counter is made large enough to vary the clock frequency over a wide range.

Disclosed anonymously.

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