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100% Error Detection Scheme for Carry Save and Carry Look-Ahead Adders

IP.com Disclosure Number: IPCOM000059867D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Shah, DA: AUTHOR

Abstract

This circuit allows 100% error detection of Carry Save and Carry Look- Ahead Adders with minimal additional circuitry. Selective duplicate circuits are utilized judiciously to enable all logic circuits involved to be checked 100%. The 100% error detection is achieved by generating parity S'p from the duplicated carries C1d-Cid from the first stage, the duplicated carries C'1d-C'i-1d from the second stage, and the parities of the three inputs to the adder, Xp, Yp, Zp, and comparing it with the parity of the output of the adder S'0-S'i . The duplicated carries in the second stage are created using duplicated carry generate (cgd1-cgdi) as well as the carry generates used internally in the adder (cg1-cgi). In Fig.

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100% Error Detection Scheme for Carry Save and Carry Look-Ahead Adders

This circuit allows 100% error detection of Carry Save and Carry Look- Ahead Adders with minimal additional circuitry. Selective duplicate circuits are utilized judiciously to enable all logic circuits involved to be checked 100%. The 100% error detection is achieved by generating parity S'p from the duplicated carries C1d-Cid from the first stage, the duplicated carries C'1d-C'i-1d from the second stage, and the parities of the three inputs to the adder, Xp, Yp, Zp, and comparing it with the parity of the output of the adder S'0-S'i . The duplicated carries in the second stage are created using duplicated carry generate (cgd1- cgdi) as well as the carry generates used internally in the adder (cg1-cgi). In Fig. 2, which is a circuit diagram of the second stage, the logic blocks that are cross- hatched denote the duplicate circuitry.

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