Browse Prior Art Database

Pulse Generating Interface Circuit

IP.com Disclosure Number: IPCOM000059869D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Faris, SM: AUTHOR

Abstract

In Josephson device circuitry, interface pulse generators are used between logic and memory portions of the circuits. Such interface circuits are necessary because Josephson logic circuits are AC powered while Josephson memory circuits are DC powered. The circuit of Fig. 1 is DC powered, accepts AC inputs, provides gain capability and high noise immunity, and a pulsed unipolar output. It is self-resetting and uses two Josephson devices DL and DR . Fig. 2 shows the threshold curves of Josephson devices D which are suitable for use herein. The circuit of Fig. 1 produces monopolar output pulses upon application of bipolar inputs, Iin, to the primary inductance Lp of the transformer. The induced current pulse Is flows through the secondary inductance Ls, the resistor Rs, and the Josephson devices DR and DL .

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Pulse Generating Interface Circuit

In Josephson device circuitry, interface pulse generators are used between logic and memory portions of the circuits. Such interface circuits are necessary because Josephson logic circuits are AC powered while Josephson memory circuits are DC powered. The circuit of Fig. 1 is DC powered, accepts AC inputs, provides gain capability and high noise immunity, and a pulsed unipolar output.

It is self-resetting and uses two Josephson devices DL and DR . Fig. 2 shows the threshold curves of Josephson devices D which are suitable for use herein. The circuit of Fig. 1 produces monopolar output pulses upon application of bipolar inputs, Iin, to the primary inductance Lp of the transformer. The induced current pulse Is flows through the secondary inductance Ls, the resistor Rs, and the Josephson devices DR and DL . The transformer is designed such that the logical "1" pulse Ir s produced by the rise of the input is sufficient to switch these devices only at the rising edge of Iin . The falling edge causes a current, If s ,low enough so that it is treated as noise and enters in the noise immunity treatment of the circuit design. The devices DR and DL are DC biased in such a way that each carries a current Ig and that either DR or DL switches first when Is + Ig exceeds the device threshold. When one device switches, its current is transferred through Ls and Rs to switch the other, finally causing 2Ig plus some overshoot to appear in load LL . The load resistors RL are designed to achieve self-resetting action of DR and DL and force the output current to decay with a time...