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Browse Prior Art Database

On-Chip Variable Strobe Time Generator

IP.com Disclosure Number: IPCOM000059870D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Kazi, AM: AUTHOR

Abstract

The technique aimed at simplifying the external timing requirements for the functional operation of high performance memory arrays is known, and contained therein basically is a Timing Generator (TG) design to be implemented on-chip to supply all array timings. This article, by contrast, concerns the further enhancement of that TG design such that it will now supply a variable data output strobe by which means it becomes possible to measure the access time of very high performance embedded arrays to a resolution of one technology block delay. The output variable strobe could therefore be varied with that resolution. Figs. 1, 2A and 2B show the time generator design described in this article. Three timings, Address-In (ADDR-IN) clock, Read/Write (R/W) clock and Data Out (D-OUT) clock, are derived from this generator design.

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On-Chip Variable Strobe Time Generator

The technique aimed at simplifying the external timing requirements for the functional operation of high performance memory arrays is known, and contained therein basically is a Timing Generator (TG) design to be implemented on-chip to supply all array timings. This article, by contrast, concerns the further enhancement of that TG design such that it will now supply a variable data output strobe by which means it becomes possible to measure the access time of very high performance embedded arrays to a resolution of one technology block delay. The output variable strobe could therefore be varied with that resolution. Figs. 1, 2A and 2B show the time generator design described in this article. Three timings, Address-In (ADDR-IN) clock, Read/Write (R/W) clock and Data Out (D-OUT) clock, are derived from this generator design. The ADDR-IN clock can also be used for Data In (D-IN) clock or, by using the same scheme as for the ADDR-IN clock, a separate D-IN clock can be generated. The particular design here disclosed has fixed ADDR-In and R/W clocks and a variable D-OUT clock, in time steps of one block delay. The technique devised to obtain one block delay timing resolution involves the selection of an appropriate phase of TG clock to propagate through the time chain for the odd or even number of blocks selected to deliver D-OUT pulses. This selection is done from the timing select bits shown in Fig. 2A. A four-bit decoder select...