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Improved Operational Amplifier Design for Analog LSI Applications

IP.com Disclosure Number: IPCOM000059899D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Berg, MD: AUTHOR [+3]

Abstract

Shown is the schematic for an operational amplifier design that works well for standard cell (masterslice) book-oriented analog LSI chips employing an ion-implanted resistor/transistor process. This design is achieved with only two transistor sizes and has a PNP/NPN ratio compatible with book-image limitations. An NPN input differential stage T1-T2 allows a higher bias current level to be employed over conventional lower beta lateral PNP stages. This current, which is mirrored by D1-T9 and D2-T10, results in a 5X improvement in slew rate over a conventional design. The use of a high FT NPN input stage also means the overall bandwidth can be greatly improved over designs which use low-FT PNP's. The offset error is reduced by T4, which cancels the T6 base-current error in the D5-T5 mirror.

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Improved Operational Amplifier Design for Analog LSI Applications

Shown is the schematic for an operational amplifier design that works well for standard cell (masterslice) book-oriented analog LSI chips employing an ion- implanted resistor/transistor process. This design is achieved with only two transistor sizes and has a PNP/NPN ratio compatible with book-image limitations. An NPN input differential stage T1-T2 allows a higher bias current level to be employed over conventional lower beta lateral PNP stages. This current, which is mirrored by D1-T9 and D2-T10, results in a 5X improvement in slew rate over a conventional design. The use of a high FT NPN input stage also means the overall bandwidth can be greatly improved over designs which use low-FT PNP's. The offset error is reduced by T4, which cancels the T6 base-current error in the D5-T5 mirror.

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