Browse Prior Art Database

Bipolar Device Incorporated Into Cmos Technology

IP.com Disclosure Number: IPCOM000059900D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Tang, DD: AUTHOR [+2]

Abstract

This article relates generally to a method for forming a bipolar device along with complementary N-channel and P-channel FETs (field-effect transistors) and more particularly to a fabrication method wherein a thin polysilicon layer is formed over a thin oxide to aid in emitter definition and to protect gate oxide quality during processing. Fig. 1 shows a cross-sectional view of an integrated circuit 1 which includes a bipolar transistor 2, a P-channel field-effect transistor 3 and an N-channel field-effect transistor 4.

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Bipolar Device Incorporated Into Cmos Technology

This article relates generally to a method for forming a bipolar device along with complementary N-channel and P-channel FETs (field-effect transistors) and more particularly to a fabrication method wherein a thin polysilicon layer is formed over a thin oxide to aid in emitter definition and to protect gate oxide quality during processing. Fig. 1 shows a cross-sectional view of an integrated circuit 1 which includes a bipolar transistor 2, a P-channel field-effect transistor 3 and an N-channel field-effect transistor 4.

Each of the transistors is separated from the others by recessed oxide (ROX) regions 5. Transistors 2,3 are disposed in an N-well 6, while transistor 4 is disposed in epitaxial layer 7. Bipolar device 2 includes a collector 8, a base 9 and an emitter contact 10, while P-channel transistor 3 includes a pair of P+ source/ drain regions 11 and a polysilicon gate 12 spaced from the surface of N-well 6 by gate oxide 13. N-channel transistor 4 includes a pair of source/drain regions 14 and a polysilicon gate 15 spaced from epitaxial layer 7 by gate oxide 16. The usual metallization has not been included. It may be easily included by a metallization and patterning step well known to those skilled in the semiconductor art. Referring now to Fig. 2A, there is shown a cross-sectional view of ROX regions 5, N-well 6 and a pair of regions between ROX regions 5 in which transistors 2,3 are to be formed. The fabrication of transistor 4 has not been specifically shown since its fabrication parallels the fabrication of transistor 3, differing only in the implantation of an N-type dopant rather than a P+ dopant as is done for transistor 3. Fig. 2A shows the structure of transistors 2,3 at an intermediate stage in their fabrication process after ROX regions 5 have been thermally grown, thin oxide layer 20 has been thermally grown and a thi...