Browse Prior Art Database

Two-Level Planar Low Temperature Interconnection

IP.com Disclosure Number: IPCOM000059908D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Bickford, HR: AUTHOR [+2]

Abstract

Wiring between non-adjacent tiles in a low temperature package may be carried out by circuits laid out on the tile baseplate and by flexible interconnections between tiles and between tile and baseplate. This eliminates the blockage which might result if such connections had to pass across intervening tiles. A planar package for small (about 50-chip) Josephson systems is shown in Figs. 1 and 2. The tiles are the first level package. Adjacent tiles 1 are interconnected with a flexible chip connector 2. Chips 3 are connected to the tiles. A personalized baseplate allows direct wiring between any two tiles and serves as a second level wiring package. By using both X and Y wiring levels on the personalized baseplate 4 it is possible to have more than one "string" of tiles.

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Two-Level Planar Low Temperature Interconnection

Wiring between non-adjacent tiles in a low temperature package may be carried out by circuits laid out on the tile baseplate and by flexible interconnections between tiles and between tile and baseplate. This eliminates the blockage which might result if such connections had to pass across intervening tiles. A planar package for small (about 50-chip) Josephson systems is shown in Figs. 1 and 2. The tiles are the first level package. Adjacent tiles 1 are interconnected with a flexible chip connector 2. Chips 3 are connected to the tiles. A personalized baseplate allows direct wiring between any two tiles and serves as a second level wiring package. By using both X and Y wiring levels on the personalized baseplate 4 it is possible to have more than one "string" of tiles. An alternate to the single part second level package is shown in Figs. 2 and 3. Here smaller second level package wiring elements 5-6, etc., are stitched together by the flexible chip connectors 2. A similar increase in wireability is realized with smaller parts. The package eliminates wiring blockage, making the planar approach extendable to larger systems with higher circuit counts. All lines are matched impedance striplines and all connectors are low inductance controlled collapse chip connectors for good electrical performance commensurate with the requirements of low temperature circuits, such as Josephson circuits. By using both X and Y wiring...