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Static Memory Cell With Inverted Flip-Flop and Diode Couplings

IP.com Disclosure Number: IPCOM000059913D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

The density of low cost, medium performance memory cells utilizing poly-silicon based technology may be significantly improved by burying the bit lines and drain line to minimize metal wiring and by employing P-N diodes for bit rail coupling. In Fig. 1, which illustrates a memory cell featuring inverted flip-flop transistors and diode couplings, the drain line (DL) 2 and bit lines (BL) 3 and 4, are buried, and Read/Write diodes 5 and 6 integrated with the polysilicon base 7. Adjacent cells and diodes on the same DL and BL's are separated by 'reach through'. Only four contacts per cell (8, 9, 10, and 11) are necessary (in the absence of metal stitchings) with the merged-transistor logic (MTL) configuration shown, as compared to the ten contacts required of a complementary-transistor-switch (CTS) cell configuration.

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Static Memory Cell With Inverted Flip-Flop and Diode Couplings

The density of low cost, medium performance memory cells utilizing poly-silicon based technology may be significantly improved by burying the bit lines and drain line to minimize metal wiring and by employing P-N diodes for bit rail coupling. In Fig. 1, which illustrates a memory cell featuring inverted flip-flop transistors and diode couplings, the drain line (DL) 2 and bit lines (BL) 3 and 4, are buried, and Read/Write diodes 5 and 6 integrated with the polysilicon base 7. Adjacent cells and diodes on the same DL and BL's are separated by 'reach through'. Only four contacts per cell (8, 9, 10, and 11) are necessary (in the absence of metal stitchings) with the merged-transistor logic (MTL) configuration shown, as compared to the ten contacts required of a complementary-transistor-switch (CTS) cell configuration. The base and collector of the left hand transistor are identified by 8 and 9 respectively, with 10 and 11 filling the same function on the right-hand transistor. Thus, at least a twofold improvement in density can be achieved from this configuration over a CTS cell design. When compared to existing MTL cell configurations, the density is slightly better and the performance significantly improved, because sense signal is directly coupled from the WL swing and the BL loadings are lighter. One operating scheme is shown in Fig. 2 which illustrates diode coupled, inverted NPN transistor cells uti...