Browse Prior Art Database

Strippable Thin Film Circuit for Electroplating of Substrates

IP.com Disclosure Number: IPCOM000059919D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Desai, KS: AUTHOR [+4]

Abstract

In the fabrication of multilayer ceramic substrates for integrated circuit chips, some designs require selective electroplating of contact gold on surface features. A process is described which uses a strippable thin film of copper to facilitate the gold plating. The multilayer ceramic substrate 1, shown in Fig. 1, includes on one surface pads 2 onto which the gold layer is to be plated, chip connector pads 3 for contacting selected areas on an integrated circuit chip, and input/output pads 4 on the opposite surface of the substrate. The body of the substrate 1 includes interconnection wiring 5 between input/output pads 4, chip connector pads 3, and pads 2. Referring to Figs. 2A-2E, a thin film 7 of copper, e.g., on the order of 1000 ˜ thick, is blanket evaporated or sputtered onto the top and bottom surfaces of substrate 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 88% of the total text.

Page 1 of 2

Strippable Thin Film Circuit for Electroplating of Substrates

In the fabrication of multilayer ceramic substrates for integrated circuit chips, some designs require selective electroplating of contact gold on surface features. A process is described which uses a strippable thin film of copper to facilitate the gold plating. The multilayer ceramic substrate 1, shown in Fig. 1, includes on one surface pads 2 onto which the gold layer is to be plated, chip connector pads 3 for contacting selected areas on an integrated circuit chip, and input/output pads 4 on the opposite surface of the substrate. The body of the substrate 1 includes interconnection wiring 5 between input/output pads 4, chip connector pads 3, and pads 2. Referring to Figs. 2A-2E, a thin film 7 of copper, e.g., on the order of 1000 ~ thick, is blanket evaporated or sputtered onto the top and bottom surfaces of substrate 1. A patterned plating resist layer 8 is then formed over the chip- connector pads 3 which are not to be plated, and the copper film 7 is etched from the top surface of the substrate, as shown in Fig. 2B. A second coating of resist 8 is formed over the pad 3 region to cover any exposed copper 7 remaining from the previous step. Alternatively, the original resist can be removed and a single coating can be applied through a larger mask opening. A layer of gold 9, is plated onto pads 2 (Fig. 2D) followed by removal of the resist 8 and etching of the remaining copper 7 from both substrate...