Browse Prior Art Database

Memory Cells With NPN Couplings

IP.com Disclosure Number: IPCOM000059935D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

Various configurations of bipolar 6-device memory cells exist which emphasize small area and speed or ease of Read and Write operation. In order to reduce the cell area on the chip, Read/Write couplings are generally accomplished in these designs by the employment of SBD's (Schottky barrier diodes), emitters or PNP devices. The 6-device medium performance memory cell described in this article uses no SBD's but achieves its small size by use of inverted NPN couplings. Fig. 1 illustrates the layout of memory cells with NPN couplings. Layout size is kept small by use of merged PNP and NPN devices (1, 2, 5 and 6), as well as integrated NPN's (3 and 4). Bases of NPN devices are connected through the poly-silicon 7. Collectors of 3 and 4 are connected to Bit Lines (BL) 8 and 9.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 73% of the total text.

Page 1 of 2

Memory Cells With NPN Couplings

Various configurations of bipolar 6-device memory cells exist which emphasize small area and speed or ease of Read and Write operation. In order to reduce the cell area on the chip, Read/Write couplings are generally accomplished in these designs by the employment of SBD's (Schottky barrier diodes), emitters or PNP devices. The 6-device medium performance memory cell described in this article uses no SBD's but achieves its small size by use of inverted NPN couplings. Fig. 1 illustrates the layout of memory cells with NPN couplings. Layout size is kept small by use of merged PNP and NPN devices (1, 2, 5 and 6), as well as integrated NPN's (3 and 4). Bases of NPN devices are connected through the poly-silicon 7. Collectors of 3 and 4 are connected to Bit Lines (BL) 8 and 9. The Word Line (WL) 10 and Drain Line (DL) 11 are placed on either side of the trench 12, in the subdiffusion layer. Oxide openings 13 and 14 and a side wall defined emitter 15 are also identified in this Figure. The operating elements in Fig. 2 retain their identities from Fig. 1, the left and right BL's being designated 8 and 9 respectively. NPN coupled cell operations follow: Standby: J8 = 0, J9 = 0, J11 = 0 V10 is kept at ~ 1.0 Volt Vsl is kept at ~ 1.6 Volt BL's 8 and 9 and DL 11 are kept above 1.0 V.; Assume device 1 is off, device 2 on, then devices 2 and 5 are in saturation. Devices 3 and 4 are off. Stability requirement is b up >
1.0 Access: 10 (WL) and 16...