Browse Prior Art Database

Single-Ended Cascode Voltage Clocked Logic With Inverts

IP.com Disclosure Number: IPCOM000059964D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Kilmoyer, RD: AUTHOR [+2]

Abstract

By eliminating the requirement for both phases in a logic tree, except where selected and still retain inverts, a substantial compression of circuitry and logic optimization may be realized. The network shown in the drawing is an example of logic group outputs A, B, and C, which feed into latch 10, and there are no inter mediate inputs to other circuits like D, E, F, and G. In this example there is no need for the logic outputs Out 1, Out 2 and Out 2 to be differential, i.e., both the true and complement phases. Therefore, one of the phases of a redundant logic string like Out 2 and others found in complete cascode voltage clocked logic (where all input logic is precharged low on a clocked pulse and logic is propagated on the low to high transition) can be eliminated.

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Single-Ended Cascode Voltage Clocked Logic With Inverts

By eliminating the requirement for both phases in a logic tree, except where selected and still retain inverts, a substantial compression of circuitry and logic optimization may be realized. The network shown in the drawing is an example of logic group outputs A, B, and C, which feed into latch 10, and there are no inter mediate inputs to other circuits like D, E, F, and G. In this example there is no need for the logic outputs Out 1, Out 2 and Out 2 to be differential, i.e., both the true and complement phases. Therefore, one of the phases of a redundant logic string like Out 2 and others found in complete cascode voltage clocked logic (where all input logic is precharged low on a clocked pulse and logic is propagated on the low to high transition) can be eliminated. Superfluous logic like "X" which feeds Latch 10 through driver 11 may be eliminated without affecting the logic being implemented. Eliminating or pruning other redundant logic branches such as intermediate output logic "sinks" and sources, such as "Y" and " Z", are considered next. This process can be repeated recursively until only a subset of the original circuit remains differential- those circuits where both phases of the outputs must be explicitly propagated. Once pruned, the remaining network is a mixture of single-ended differential logic circuits where all signals are propagated by positive-going transitions. The logic may be considered...