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Underlayer for Polycide Process

IP.com Disclosure Number: IPCOM000059965D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Ahn, KY: AUTHOR [+4]

Abstract

Described below is a process used in forming the gate of a self-aligned MOSFET. More specifically, the process disclosed prevents delamination of a refractory metal silicide layer on a polysilicon layer of the gate terminal by providing an intermediary layer of titanium. Refractory metal silicides (such as tungsten silicate) are used on polysilicon gates in VLSI applications to increase conductivity and are necessary in many applications. However, interfacial stress at the polysilicon-metal silicate interface often results in delamination. One solution to the above problem is to provide excess silicon to the silicide layer to yield a non-stoichiometric composition to increase adhesion. This solution, however, exhibited lower conductivity and greater variation in etching characteristics.

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Underlayer for Polycide Process

Described below is a process used in forming the gate of a self-aligned MOSFET. More specifically, the process disclosed prevents delamination of a refractory metal silicide layer on a polysilicon layer of the gate terminal by providing an intermediary layer of titanium. Refractory metal silicides (such as tungsten silicate) are used on polysilicon gates in VLSI applications to increase conductivity and are necessary in many applications. However, interfacial stress at the polysilicon-metal silicate interface often results in delamination. One solution to the above problem is to provide excess silicon to the silicide layer to yield a non-stoichiometric composition to increase adhesion. This solution, however, exhibited lower conductivity and greater variation in etching characteristics. Control of the excess Si was also found to be a problem. This disclosure, however, provides the desired alternative solution to increase adhesion without loss of conductivity. Referring to Fig. 1, in the process disclosed herein, a thin titanium (Ti) layer (10 to 50 nm) is deposited on the polysilicon layer by sputtering, evaporation or chemical vapor deposition (CVD). Then, stoichiometric tungsten silicide (WSi2) is deposited on the Ti layer by CVD. Finally, the three layers are annealed and patterned to produce the result schematically illustrated in Fig. 2. The intermediary Ti layer allows for easy nucleation of the WSi2 . More importantly, the T...