Browse Prior Art Database

Latch-Up Free CMOS Structure

IP.com Disclosure Number: IPCOM000059967D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Lai, FS: AUTHOR

Abstract

This article relates generally to integrated circuit construction and, more particularly, to a method of constructing CMOS devices to prevent conduction latch-up. Unwanted conduction latch-up due to minority carriers injected by forward-biased emitter-base junctions can be prevented by forming a recessed n-channel CMOS structure to block the carriers. Referring to Fig. 1, p- substrate 1 is implanted with a high dose of arsenic over its entire surface to form n+ layer 2. An epitaxial n- layer 3 is grown on top of the wafer, and photoresist 4 is exposed and developed to define the p-channel device region. Reactive ion etching with a FREON 12* and oxygen process is used to remove the exposed n- epitaxial layer 3 and underlying n+ layer 2.

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Latch-Up Free CMOS Structure

This article relates generally to integrated circuit construction and, more particularly, to a method of constructing CMOS devices to prevent conduction latch-up. Unwanted conduction latch-up due to minority carriers injected by forward-biased emitter-base junctions can be prevented by forming a recessed n- channel CMOS structure to block the carriers. Referring to Fig. 1, p- substrate 1 is implanted with a high dose of arsenic over its entire surface to form n+ layer 2. An epitaxial n- layer 3 is grown on top of the wafer, and photoresist 4 is exposed and developed to define the p-channel device region. Reactive ion etching with a FREON 12* and oxygen process is used to remove the exposed n- epitaxial layer 3 and underlying n+ layer 2. Conventional CMOS processes are then employed to fabricate the p- channel devices on n- epitaxial layer 3 and the n-channel devices on p- substrate 1, as shown in Fig. 2. Both the electron and hole minority carriers will be blocked by n+ layer 2 to eliminate the positive feedback phenomenon. Coverage of the step due to height difference can be accomplished by a low temperature oxide planarization method and extra mask for the contact hole opening. * Trademark of E. I. du Pont de Nemours & Co.

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