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Browse Prior Art Database

CMOS On-Chip Starter Circuit for Substrate Bias Generator

IP.com Disclosure Number: IPCOM000059968D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Dreibelbis, DH: AUTHOR

Abstract

This on-chip starter circuit design insures that a substrate voltage generator starts every time, that a voltage doubler sees mature voltages at turn-on time, and that the starter circuit is returned to a quiescent state once its function is complete. In many cases it is imperative that on-chip bias generators start when voltage is applied to the chip to prevent latch-up. It is also important for proper operation of the generator's voltage doubler (30-34 and T12-T14) that the pump capacitors 33 and 34 reach mature voltage levels. This will not happen if more than one switching transient is travelling through the ring oscillator (20-28). Also, the on-chip power consumption may be contained by returning the starter circuit (T1-T11) to the off state once the substrate bias generator is functioning.

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CMOS On-Chip Starter Circuit for Substrate Bias Generator

This on-chip starter circuit design insures that a substrate voltage generator starts every time, that a voltage doubler sees mature voltages at turn-on time, and that the starter circuit is returned to a quiescent state once its function is complete. In many cases it is imperative that on-chip bias generators start when voltage is applied to the chip to prevent latch-up. It is also important for proper operation of the generator's voltage doubler (30-34 and T12-T14) that the pump capacitors 33 and 34 reach mature voltage levels. This will not happen if more than one switching transient is travelling through the ring oscillator (20-28). Also, the on-chip power consumption may be contained by returning the starter circuit (T1-T11) to the off state once the substrate bias generator is functioning. The complementary metal-oxide semiconductor (CMOS) circuit design illustrated achieves all of these objectives. As VDD is ramped from 0-5 volts (turn-on), nodes A, B, C and D have a tendency to track it. The objective is to hold ENABLE low until transients from turn-on have stabilized, and then set ENABLE. As few devices as possible are used in the start circuit (T1-T11) to keep it simple and reliable. By adjusting the width/length (W/L) ratio of the different devices (see the table below), a small time delay is realized which is needed to achieve node voltages (A-D) during turn-on that is contrary to those ultimat...