Browse Prior Art Database

Low Input Swing Bipolar/Field Effect Transistor Receiver

IP.com Disclosure Number: IPCOM000059970D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Craig, WJ: AUTHOR [+3]

Abstract

A high speed voltage level conversion (from emitter-coupled logic (ECL) levels to complementary metal-oxide-silicon (CMOS) levels) using very little power is featured in this article. In this level conversion, an all field-effect transistor (FET) receiver is either not sensitive enough for ECL levels or too slow when differential sensing is used to enhance sensitivity. By using a bipolar differential pair T5 and T6 (shown in the figure) for input sensitivity and then converting the signal to full CMOS levels with a hybrid bipolar-FET stage T2 and T3, a high speed ECL to CMOS level conversion is possible with very little power. The maximum signal that may be generated across resistor R1 is 1.0 volt because larger levels will cause saturation and degrade the performance of the bipolar differential pair. The 1.

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Low Input Swing Bipolar/Field Effect Transistor Receiver

A high speed voltage level conversion (from emitter-coupled logic (ECL) levels to complementary metal-oxide-silicon (CMOS) levels) using very little power is featured in this article. In this level conversion, an all field-effect transistor (FET) receiver is either not sensitive enough for ECL levels or too slow when differential sensing is used to enhance sensitivity. By using a bipolar differential pair T5 and T6 (shown in the figure) for input sensitivity and then converting the signal to full CMOS levels with a hybrid bipolar-FET stage T2 and T3, a high speed ECL to CMOS level conversion is possible with very little power. The maximum signal that may be generated across resistor R1 is 1.0 volt because larger levels will cause saturation and degrade the performance of the bipolar differential pair. The
1.0 volt swing is shifted N 0.7 volt by the bipolar device T1 and the signal at the gate of P-channel FET T2 is approximately at the threshold voltage point and swings to about 1.0 volt of overdrive. The bipolar npn transistor T3 discharges node A when the gate of T2 is at an up level. The output signal is converted to full CMOS levels of 1.4 volts and 2.2 volts by means of an inverter 10 having N and P transistors fed by node A.

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