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Precise Trigger and Voltage Tracking Delay Circuit

IP.com Disclosure Number: IPCOM000059974D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Heudorfer, P: AUTHOR [+3]

Abstract

This article describes a method for maintaining proper delays between circuits with varying supply voltages through the utilization of a Schmitt trigger and a depletion device/capacitor network instead of a resistor/capacitor network in a delay stage. The circuit shown in the figure consists of two main sections: a Schmitt trigger (T1, T2, T3 and T4) which fires at a preselected input voltage and a delay section (T5 and T6). Initially, nodes A and B are charged through devices T1 and T5 and the output is held at ground by T9. With a positive input signal on T3, node A discharges to ground through devices T2 and T3 when the input signal reaches the trigger point of the Schmitt trigger. The delay section (T5 and T6) takes over at this point, and node B starts to discharge through device T5 which is in saturation.

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Precise Trigger and Voltage Tracking Delay Circuit

This article describes a method for maintaining proper delays between circuits with varying supply voltages through the utilization of a Schmitt trigger and a depletion device/capacitor network instead of a resistor/capacitor network in a delay stage. The circuit shown in the figure consists of two main sections: a Schmitt trigger (T1, T2, T3 and T4) which fires at a preselected input voltage and a delay section (T5 and T6). Initially, nodes A and B are charged through devices T1 and T5 and the output is held at ground by T9. With a positive input signal on T3, node A discharges to ground through devices T2 and T3 when the input signal reaches the trigger point of the Schmitt trigger. The delay section (T5 and T6) takes over at this point, and node B starts to discharge through device T5 which is in saturation. As node B reaches the threshold voltage VT of T5, device T5 enters the linear region and node B approaches the VT of T9. As T9 turns off, the output will rise. The decay of node B is linear and can be determined by the Beta of device T5 and the capacitance of T6. This circuit has the following features: 1) Better delay stage to circuit delay tracking, which shortens the worst- case performance. 2) The delay increases with an increase in voltage. 3) The area required for the delay circuit is considerably smaller than an equivalent RC network

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