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Decoder Circuit for Processing Logically Redundant Differential Pair Inputs to Static CMOS Circuits

IP.com Disclosure Number: IPCOM000059975D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Hickson, JB: AUTHOR [+2]

Abstract

This publication describes a circuit that provides valid outputs for use by static CMOS circuits, from logically redundant DCVS inputs which may be partially erroneous. VLSI (very large-scale integration) may incorporate redundant circuitry to improve yield, reliability, costs, and other factors. One part of a VLSI chip may include redundant units "A" and "B", which generate signals to be used in unit "C". The units "A" and "B" may generate both true and complement signals, which is always the case for DCVS (differential cascode voltage switch) circuits and is sometimes the case for other implementations too. Unit "C", as shown in Fig. 1, may incorporate the static CMOS decoder circuit described here to analyze the redundant differential inputs from units "A" and "B".

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Decoder Circuit for Processing Logically Redundant Differential Pair Inputs to Static CMOS Circuits

This publication describes a circuit that provides valid outputs for use by static CMOS circuits, from logically redundant DCVS inputs which may be partially erroneous. VLSI (very large-scale integration) may incorporate redundant circuitry to improve yield, reliability, costs, and other factors. One part of a VLSI chip may include redundant units "A" and "B", which generate signals to be used in unit "C". The units "A" and "B" may generate both true and complement signals, which is always the case for DCVS (differential cascode voltage switch) circuits and is sometimes the case for other implementations too. Unit "C", as shown in Fig. 1, may incorporate the static CMOS decoder circuit described here to analyze the redundant differential inputs from units "A" and "B". Use of this circuit will enable unit "C" to function successfully even when some failures occur in units "A" and "B", so that unit "C" will continue to provide correct results even when some of its inputs are not valid. One of the most appropriate circuit technologies for this decoder circuit is static, fully complementary CMOS. This technology is employed in the description of the circuit of this publication. Variations of this circuit may be implemented in other technologies by those skilled in the art. DCVS is a technology wherein each circuit generates a "differential pair" of signals whose values should be opposite. That is, when member 1 of the pair has a "high" voltage level, then member 2 should have a "low" voltage level, and when member 1 is "low", then member 2 should be "high". Another characteristic of this technology is that when a circuit fails to produce a pair of valid signals, it almost always produces a pair of signals with equal voltage levels ("high" and "high", or "low" and "low"). This technology is assumed to be used in units "A" and "B" to provide the redundant complementary signals. Other technologies can easily provide complementary outputs by adding inverters, and many different circuit families can coexist on a VLSI chip. Fig. 1 shows an example of the application of the static CMOS decoder. Two redundant DCVS logical units generate a differential pair of signals to be used by a static CMOS logical unit. The two output signals from logical unit "A" are a differential pair, which can be called "A" and "Abar". Similarly, the outputs of logical unit "B" are called "B" and "Bbar". The decoder circuit in logical unit "C" is to produce a differential pair which can be called "R" and "Rbar". The logical function required by the decoder circuit is fully described by the annotated "Truth Table" set forth below. The reduced logical expression for each of the outputs is: R = (A v Abar) (B v Bbar)

Rbar = ( A v Abar) ( B v Bbar) where "v" is the logical "OR", " " is the logical...