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High Performance CMOS Logic Gate

IP.com Disclosure Number: IPCOM000059977D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Dovek, MM: AUTHOR [+3]

Abstract

In this publication an improved CMOS logic gate structure is described which is an alternative solution to the slow rise delay of large CMOS logic structures caused by the low hole mobility and the large p- channel device body effect, and which does not require an increase in chip (or gate) area. The improved logic gate replaces the complicated pullup structure with a p-channel device whose gate is grounded. Essentially this is the CMOS implementation of an nMOS gate with a depletion-type pullup. This will result in a faster rise delay since it resolves the problem of large p-channel device body effect. Unfortunately, the grounded gate alone is not sufficient to reduce the delay to the order of 6.5 nanoseconds that would be achieved with broken up gates.

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High Performance CMOS Logic Gate

In this publication an improved CMOS logic gate structure is described which is an alternative solution to the slow rise delay of large CMOS logic structures caused by the low hole mobility and the large p- channel device body effect, and which does not require an increase in chip (or gate) area. The improved logic gate replaces the complicated pullup structure with a p-channel device whose gate is grounded. Essentially this is the CMOS implementation of an nMOS gate with a depletion-type pullup. This will result in a faster rise delay since it resolves the problem of large p-channel device body effect. Unfortunately, the grounded gate alone is not sufficient to reduce the delay to the order of 6.5 nanoseconds that would be achieved with broken up gates. This delay can only be achieved after the capacitance of the n-side of the structure is partially eliminated. Referring to the figure, an n-channel device T1 whose gate is controlled by the feedback inverter (T2 and T3) is inserted between the output node (ROUTPUT) and the pulldown structure. When the pulldown structure turns on, a path between the node-OUTPUT and ground is established. This discharges node- OUTPUT to ground, turning devices T1 on and T5 off. Node-ROUTPUT also discharges to ground through device T1. The circuit reaches a steady-state condition when node-OUTPUT and node-ROUTPUT are at a potential (near ground) determined by the impedance of the pulldown structure a...