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Interface Between a Host Processor and an I/O Processor in a Multiprocessor System

IP.com Disclosure Number: IPCOM000059986D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Carter, DW: AUTHOR [+5]

Abstract

This article describes a method of interface control between a control storage processor (CSP--host) and a file storage processor (FSP--I/O processor). Processor-to-processor communication, where one is an input/output (I/O) processor, requires speed and efficiency to offload the CPU cycle loads. Because processing time is an important factor in the operation of computer systems, this article describes a method of offloading the host processor to increase system response time and functional capabilities. Without the FSP (I/O processor), the disk and diskette are connected directly to the CSP channel. With the FSP, the disk, diskette, and tape exist under the FSP. With these I/O devices under the FSP, we reduce the CPU cycle loading on the CSP.

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Interface Between a Host Processor and an I/O Processor in a Multiprocessor System

This article describes a method of interface control between a control storage processor (CSP--host) and a file storage processor (FSP--I/O processor). Processor-to-processor communication, where one is an input/output (I/O) processor, requires speed and efficiency to offload the CPU cycle loads. Because processing time is an important factor in the operation of computer systems, this article describes a method of offloading the host processor to increase system response time and functional capabilities. Without the FSP (I/O processor), the disk and diskette are connected directly to the CSP channel. With the FSP, the disk, diskette, and tape exist under the FSP. With these I/O devices under the FSP, we reduce the CPU cycle loading on the CSP. The interface between the CSP and the FSP is controlled by using interrupts and status bits that can be accessed by both processors. Whenever a status bit is set, an interrupt to one of the processors is initiated. The following description is depicted in the figure, with the command flow and all status bits shown. The status bits are set and reset by the processor, as shown. When the CSP sends a command request to the FSP, the CSP sets a 'command pending' status. This condition interrupts the FSP, indicating that a command DCB is built. This block contains all the information the FSP needs for operation. The FSP retrieves the command DCB from the CSP and then sets a 'command DCB transfer complete' status. This condition interrupts the CSP, indicating that the DCB has been retrieved and that the CSP can build another. When the I/O operation finishes, the FSP sends the completed DCB to the post-DCB in the CSP and sets a 'post DCB transfer complete' status. This interrupts the CSP, indicating that a post- DCB has been returned. This block contains all of the information about the completed I/O operation in the FSP. When the data has been extracted from the post-DCB, the CSP sets a 'DCB posted' status. This interrupts the FSP, indicating that another completed operation can be sent across the interface. One bit in the CSP and three bits in the FSP also help control the interface.

In the CSP, while the interface is busy transferring a command DCB to the FSP, the 'dcb busy' flag is set. In the FSP, while the interface is busy transferring data back to the CSP, 'the post DCB busy' flag is set. The 'command pending' flag is set if the CSP has signaled that a command DCB is built but no FSP storage is available to save it. It remains set and no DCBs are brought down until a storage area frees and this bit is reset. The 'data xfer op in progress' flag is set, indicating the interface is busy transferring data associated with some function in the FSP. The supervisor call (SVC) processor calls an I/O exit routine when a command is to be sent to the FSP. If 'dcb busy' is not set, queue the action control elemen...