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Medium-Power, Minimal-Area Clamping Circuits for Bipolar Application

IP.com Disclosure Number: IPCOM000059995D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+5]

Abstract

Two clamping circuits are disclosed in this article which provide good clamping action, a stable output level, and substantial area savings over alternatives. Fig. 1 illustrates a medium-power undershoot clamping circuit designed to prevent an excessively negative undershoot voltage from appearing on a transmission line driven by bipolar off-chip driver circuits. It is implemented as shown in Fig. 2. The output of this clamping circuit may be applied to each receiver input used in a long- line transmission line application, without concern for Beta degradation or breakdowns due to high line voltage, due to the series connection of transistor T1 and the Schottky barrier diode (SBD) S2. The circuit operates as follows: R1, S1, and D1 establish the bias circuit for the clamping circuit. Assuming Vbe = 0.8 volt and Vsbd = 0.

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Medium-Power, Minimal-Area Clamping Circuits for Bipolar Application

Two clamping circuits are disclosed in this article which provide good clamping action, a stable output level, and substantial area savings over alternatives. Fig. 1 illustrates a medium-power undershoot clamping circuit designed to prevent an excessively negative undershoot voltage from appearing on a transmission line driven by bipolar off-chip driver circuits. It is implemented as shown in Fig. 2. The output of this clamping circuit may be applied to each receiver input used in a long- line transmission line application, without concern for Beta degradation or breakdowns due to high line voltage, due to the series connection of transistor T1 and the Schottky barrier diode (SBD) S2. The circuit operates as follows: R1, S1, and D1 establish the bias circuit for the clamping circuit. Assuming Vbe = 0.8 volt and Vsbd = 0.6 volt, 1.4 volts is always present at the base of T1, with current flowing from the +5.0 volt supply through the bias circuit to ground. The nominal power dissipation of the bias circuit is 3.6 mW. By increasing the value of the resistor R1 to 10 kOhms this standby power dissipation is reduced to 1.8 mW. In order to forward bias the base of T1 and S2, the output need only go 1.4 volts lower in potential than the base of T1, or to 0 volts. The clamp therefore essentially clamps to 0 volts in the DC case, supplying current through the transistor action of T1. The resistor R2 prevents any floating nodes so that a high line voltage along with the presence of R2 insures that S2 is reverse-biased (0.6 volt at the emitter of T1), and not the emitter-base junction of T1. Nominal power dissipation of R2 is 0.128 mW. In general, prevention of excessive negative v...