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Semi-Self-Aligned Contact for Semiconductor Circuits

IP.com Disclosure Number: IPCOM000060029D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Bausmith, RC: AUTHOR [+3]

Abstract

A method is shown for forming a semi-self-aligned contact between upper levels of wiring and the gate electrode of a field-effect transistor (FET), resulting in improved densities. Dense CMOS random-access memories and logic circuits require many contacts between the FET gate electrodes and upper levels of wiring. These contacts consume a large amount of the available chip area, so that device density consistent with minimum lithographic dimensions cannot be fully realized. Fig. 1 shows the cross-section of a gate region of an FET. A gate electrode 10 is patterned atop an oxide layer 8 formed on the silicon wafer 11. The exposed surfaces of gate electrode 10 are oxidized to form oxide layer 12.

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Semi-Self-Aligned Contact for Semiconductor Circuits

A method is shown for forming a semi-self-aligned contact between upper levels of wiring and the gate electrode of a field-effect transistor (FET), resulting in improved densities. Dense CMOS random-access memories and logic circuits require many contacts between the FET gate electrodes and upper levels of wiring. These contacts consume a large amount of the available chip area, so that device density consistent with minimum lithographic dimensions cannot be fully realized. Fig. 1 shows the cross-section of a gate region of an FET. A gate electrode 10 is patterned atop an oxide layer 8 formed on the silicon wafer 11. The exposed surfaces of gate electrode 10 are oxidized to form oxide layer 12. A thick layer (1-2 mm) of photoresist 13 is applied, and the photoresist is etched back until the top surface 14 of the oxidized polysilicon/polycide gate electrode 10 is exposed while leaving a thin layer of photoresist 13 over the adjacent areas. Next, a non-erodible mask layer 15 is deposited on photoresist 13. Alternatively, the etched-back photoresist 13 could be hardened so that it is no longer sensitive to ultraviolet light. Fig. 2 shows a cross-section of the gate electrode region after a second photoresist layer 16 is formed and then patterned over the gate region. The non-erodible masking material 15 (if used), the etched- back first layer of photoresist 13 and the oxide 12 over the gate electrode 10 are then s...