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Circuit Synthesis Algorithm/Program

IP.com Disclosure Number: IPCOM000060046D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Doerre, G: AUTHOR

Abstract

A method for grouping devices into appropriate circuits from layout data provides an improved method for individual circuit analysis, greatly improving the efficiency of automatic simulation programs. After design, a custom memory layout may be segmented according to a schematic rather than by physical criterion. This technique is more efficient than by a manual operation and may be performed by operators without circuit design skills. In the layout database of the Integrated Circuit Design System (ICDS) being used, there are provisions in the data structure for naming each wiring net and in a typical random-access memory design about 25% of the wiring nets are named. The rest are unnamed. The unnamed wiring nets are contained within individual circuits, and the named nets connect different circuits.

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Circuit Synthesis Algorithm/Program

A method for grouping devices into appropriate circuits from layout data provides an improved method for individual circuit analysis, greatly improving the efficiency of automatic simulation programs. After design, a custom memory layout may be segmented according to a schematic rather than by physical criterion. This technique is more efficient than by a manual operation and may be performed by operators without circuit design skills. In the layout database of the Integrated Circuit Design System (ICDS) being used, there are provisions in the data structure for naming each wiring net and in a typical random-access memory design about 25% of the wiring nets are named. The rest are unnamed. The unnamed wiring nets are contained within individual circuits, and the named nets connect different circuits. Because of this distinction, the algorithm shown in the figure has been used to group devices (FETs, capacitors and resistors) schematically. The layout data associated with these devices may be extracted automatically from the total design and used either for macro design purposes or for simulation deck generation. The algorithm is executed once for each wiring net. With each execution of loop 10, more devices and unnamed nets corresponding to a circuit are found until the entire circuit is found. The algorithm anchors each circuit with an unnamed wiring net and devices connected to named nets only will not be included in any circ...