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Latch-Up Free CMOS Structure

IP.com Disclosure Number: IPCOM000060058D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Hsu, Y: AUTHOR

Abstract

This article relates generally to integrated circuit fabrication and, more particularly, to a construction technique for preventing active device latch-up. Full dielectric isolation of active CMOS devices forestalls conductive latch-up and is achieved by using oxide as a mask for growing selective epitaxy and oxygen ion implantation to produce an insulator. In Fig. 1, a layer 1 of oxide is grown on a p or n type silicon substrate 2 and selectively removed via photoresist patterning to expose the substrate. A thin epitaxial layer 3, indicated by dashed lines, is selectively grown on the exposed silicon using oxide 1 as a mask. Oxygen is implanted into the epitaxial layer 3 to form a buried oxide layer 4 approximately 3000 thick and about 2000 ˜ down from the surface of the layer 3.

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Latch-Up Free CMOS Structure

This article relates generally to integrated circuit fabrication and, more particularly, to a construction technique for preventing active device latch-up. Full dielectric isolation of active CMOS devices forestalls conductive latch-up and is achieved by using oxide as a mask for growing selective epitaxy and oxygen ion implantation to produce an insulator. In Fig. 1, a layer 1 of oxide is grown on a p or n type silicon substrate 2 and selectively removed via photoresist patterning to expose the substrate. A thin epitaxial layer 3, indicated by dashed lines, is selectively grown on the exposed silicon using oxide 1 as a mask. Oxygen is implanted into the epitaxial layer 3 to form a buried oxide layer 4 approximately 3000 thick and about 2000 ~ down from the surface of the layer 3.

The wafer is thereafter annealed and briefly dipped in an etchant to remove residual surface oxide. Selective epitaxy with the desired resistivity is then grown at 5 (Fig. 2) with oxide layer 1 as a mask.

This results in silicon islands surrounded by oxide to form full dielectric isolation. Standard CMOS processes can be resumed to achieve latch-up free devices, as shown in Fig. 3.

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