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Redundancy Book for VLSI Chips

IP.com Disclosure Number: IPCOM000060065D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Boertzel, M: AUTHOR [+4]

Abstract

Proposed is a special design of a "redundancy book" for VLSI chips, such as gate arrays, master images or m-processors, with a plurality of logic gates and memory bits. This book follows the design rules for logic books and comprises a certain number of fuses.

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Redundancy Book for VLSI Chips

Proposed is a special design of a "redundancy book" for VLSI chips, such as gate arrays, master images or m-processors, with a plurality of logic gates and memory bits. This book follows the design rules for logic books and comprises a certain number of fuses.

The fuses are connected to VH or GND on one side and to LSTs (logic service terminals) on the other. The LSTs are coded into the automatic physical design system such that the wiring program can pick up the fuses when they are required by an array macro. The other side of the array macro is provided with defined LSTs for connecting the fuses. The array macro receives the redundancy addresses from the redundancy book. By means of the address information, the array macro may deselect a defective part, such as a word line, and select a redundant part. One or more redundancy books may be used, depending upon the respective part number. The redundancy books are permanently fixed to, say, a chip corner. This is a fixed location for all part numbers to permit fuse blowing with one fixed adjustment of the laser tool. Under these circumstances, the special ground rules for the design of the fuses can be readily followed. The fixed area in a chip corner does not really belong to the logic circuit region of the chip. Wiring and power distribution in the chip corner are not required. Fig. 1 shows the physical fuse layout and Fig. 2 the equivalent circuit of one fuse with resistor R and am...