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Dual Processing for Signal Processors

IP.com Disclosure Number: IPCOM000060132D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR

Abstract

In general, in signal processors data memory and instruction memory have separate busses to allow simultaneous accesses to be made. The minimum cycle time is dependent on the access time and on internal cycle time. To increase the processing power, the processors are duplicated and means are provided to facilitate the exchange between the two processors sharing the same data memory. The contention problem is solved by multiplexing the random-access memory (RAM). Processor 1 has a complete cycle to perform internal processing; the second half of the cycle is used for accessing to the RAM. Processor 2 cycle is delayed by one half of a cycle to allow the RAM to be accessed when processor 1 is disconnected.

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Dual Processing for Signal Processors

In general, in signal processors data memory and instruction memory have separate busses to allow simultaneous accesses to be made. The minimum cycle time is dependent on the access time and on internal cycle time. To increase the processing power, the processors are duplicated and means are provided to facilitate the exchange between the two processors sharing the same data memory. The contention problem is solved by multiplexing the random- access memory (RAM). Processor 1 has a complete cycle to perform internal processing; the second half of the cycle is used for accessing to the RAM. Processor 2 cycle is delayed by one half of a cycle to allow the RAM to be accessed when processor 1 is disconnected. The RAM address bus and the data bus of the processors are dotted, and the flip-flop control of the tri-state drivers D allows the multiplexing to be done. The parameter exchange from one program in Processor 1 to another program in Processor 2 is done in the same way as with one processor, i.e., a dedicated register in RAM is used. Thus, the program architecture is not changed, the instruction program is only located in another processor. A monitoring program is used for running several programs or routines at the same time.

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