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Threaded Code Interpreter for Object Code

IP.com Disclosure Number: IPCOM000060142D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Lang, TG: AUTHOR [+3]

Abstract

A method is described to simulate or emulate the functions of an older processor's instruction set with software or microcode. The simulator has two basic steps: 1. Interpret the object code of an instruction to determine its function. 2. Perform an equivalent function. Since most processors have instructions which perform similar functions, step 2 can usually be handled with one instruction or, at worst, a short sequence of instructions. In the case where the new processor has a very simple instruction set, and the old processor has a complex instruction set, simulating the functions of the commonly used instructions requires an average of 5 to 15 new instructions. Due to the complex nature of the old instruction set, however, up to 150 new instructions may be required to interpret an old instruction (step 1).

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Threaded Code Interpreter for Object Code

A method is described to simulate or emulate the functions of an older processor's instruction set with software or microcode. The simulator has two basic steps: 1. Interpret the object code of an instruction to determine its function. 2. Perform an equivalent function. Since most processors have instructions which perform similar functions, step 2 can usually be handled with one instruction or, at worst, a short sequence of instructions. In the case where the new processor has a very simple instruction set, and the old processor has a complex instruction set, simulating the functions of the commonly used instructions requires an average of 5 to 15 new instructions. Due to the complex nature of the old instruction set, however, up to 150 new instructions may be required to interpret an old instruction (step 1). Clearly, the overhead required for interpretation of the object code consumes the majority of the time spent during simulation. This overhead is sufficiently large as to make the traditional simulation approach impractical. To reduce the overhead of simulation, the time spent interpreting object code is minimized. This can be done by implementing a "Threaded Code" interpreter, or incremental compiler. The simulator attempts to remember the results of previously interpreted object code so that repetitively executed instructions do not need to be re-interpreted. Two data structures are required; an area to contain the simulated memory of the old machine and an area containing "cells." Each cell contains 8 bytes and there is one cell for each byte of simulated memory. This data structure can become quite large; it is assumed that the new processor has a large virtual memory to contain the data. When the simulated machine is started up, or IPLed (initial program loaded), the cells are initialized to contain two 4-byte instructions. The first instruction is a branch to the interpreter, and the second loads the simulated memory address into a register for use by the interpreter. The branch instruction utilizes the "branch and execute" capability to execute the next sequential instruction while the branch is being processed, so that the time required to execute the next instruction is effectively zero. To start simulating instructions, the address of the first instruction in simulated memory is multiplied by 8, yielding the offset of the cell which corresponds to the first (or only) byte of the instruction. Control is transferred to this address, which results in the interpreter being called. The interpreter examines the object code and builds a "service routine" of one or more new instructions which simulate the function of the instruction and inserts these instructions into the cell(s). If the old instruction occupies one byte, only one cell can be used. If the instruction occupies two bytes, two contiguous cells are used, etc. Each cell can contain any combination of new instruct...