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Power-On Clamp Circuit for On-Chip Biased N-Wells

IP.com Disclosure Number: IPCOM000060152D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Cottrell, PE: AUTHOR [+2]

Abstract

A power-up clamp circuit is employed to obtain short charge-up time of N-wells biased to a voltage higher than the most positive supply voltage (Vh). The power-up clamp is used in complementary metal oxide silicon (CMOS) dynamic random-access memory (DRAM). The clamp circuit prevents the parasitic vertical PNP transistors from turning on and presents a high impedance when the N-well charging (pump) circuit raises the N-well above the supply voltage. Referring to the figures, the characteristics of the clamp transistor 2 prevent the parasitic vertical transistor 4 from turning on. This clamp 2 is an enhanced lateral PNP transistor wherein the emitter is connected to the Vh supply and the base and collector are connected to the N-well 60 (and the N-well to substrate capacitance C) that is to be charged above Vh.

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Power-On Clamp Circuit for On-Chip Biased N-Wells

A power-up clamp circuit is employed to obtain short charge-up time of N-wells biased to a voltage higher than the most positive supply voltage (Vh). The power-up clamp is used in complementary metal oxide silicon (CMOS) dynamic random-access memory (DRAM). The clamp circuit prevents the parasitic vertical PNP transistors from turning on and presents a high impedance when the N-well charging (pump) circuit raises the N-well above the supply voltage. Referring to the figures, the characteristics of the clamp transistor 2 prevent the parasitic vertical transistor 4 from turning on. This clamp 2 is an enhanced lateral PNP transistor wherein the emitter is connected to the Vh supply and the base and collector are connected to the N-well 60 (and the N-well to substrate capacitance C) that is to be charged above Vh. Note that the substrate ground connection node 16 is not shown in the cross section. This over-voltage is supplied to Node 6 from the high impedance pump circuit 7. The P+ diffusion 8 in the floating N-well 60 is at a potential less than Vh. This potential difference is equal to the drain-source potential of diffusion 12 in the P channel bit line restore device 14 formed in N-well 10, and results in considerably less current as compared to the current in the forward biased diode in the clamp transistor 2. The characteristics desirable in the clamp transistor 2 are low base-emitter voltage (Vbe) and high gain...