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High Level Language for Creating Analog TEST System Programs

IP.com Disclosure Number: IPCOM000060154D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Jordan, DL: AUTHOR

Abstract

A high level input language and test data supply system for creating test programs adaptable to a variety of semiconductor chip testers is described. The main driving software is tester independent with calls to user-defined subroutines in the syntax of the tester being addressed. This language conveys the general test conditions via a word processor, e.g., TSO (Time Sharing Option), to create a standard 80- character data set similar to old card input languages, e.g., columns 1-72 for data and 73-80 for normal TSO dataset statistics and line numbers. The input allows for liberal use of blanks and comments for readability and clarification, with general keywords and delimiters to define the testing to be done.

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High Level Language for Creating Analog TEST System Programs

A high level input language and test data supply system for creating test programs adaptable to a variety of semiconductor chip testers is described. The main driving software is tester independent with calls to user-defined subroutines in the syntax of the tester being addressed. This language conveys the general test conditions via a word processor, e.g., TSO (Time Sharing Option), to create a standard 80- character data set similar to old card input languages, e.g., columns 1-72 for data and 73-80 for normal TSO dataset statistics and line numbers. The input allows for liberal use of blanks and comments for readability and clarification, with general keywords and delimiters to define the testing to be done.

The language is broken up into several key sections, each designated by a dollar sign $ followed by a keyword for that section. The normal flow of a PNP (Part Number Program) by sections might be as follows: $ HEADER Title descriptions for documentation primarily. $ EC LEVELS Levels of engineering change. $ PINS Chip pads or module pins. $ LOADS Loading requirements. $ POWER SUPPLIES High current chip supplies other than ground. $ INPUTS Define high and low pin voltage states. $ FORCE Actually apply voltage/current to pins. $ TEST Measure conditions, high/low limits, comments. $ NOTE 1 Special footnote about test requirements. $ END NOTE 1 $ FORCE Force changes between tests. $ TEST Further testing conditions. $ FORCE Actually apply voltage/current to pins. $ RUN PATTERNS Functional pattern testing. $ PATTERNS Define pattern pins/small patterns themselves. $ END The majority of the test specification is defined by alternating back and forth between new forced conditions and measuring against expected results under the new conditions. The flow chart shows how this language source from INPUT file 1 is expanded to result in the tester PNP. Each of the programs 2, 4, 6, and 8 through which the...