Browse Prior Art Database

Incrementer With Row-To-Column Address Strobe Carry-In Capability

IP.com Disclosure Number: IPCOM000060163D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Gray, KS: AUTHOR [+2]

Abstract

This incrementer circuit allows the chip's full word length address inputs to be incremented by one without external hardware or software requirements. The circuit allows the high-order carry-out of the row address strobe (RAS) to be the low-order carry-in of the column address strobe (CAS) incrementation. Systems requiring such an operation, benefit in performance by using this incrementer circuit. As shown in the diagram, the incrementer 32 uses two flip-flop circuits. Depletion loads are shown, but any type of load device can be substituted. Two timing pulses from the primary memory chip 20 are required: a) a RAS true/complement (T/C) latching pulse 22 which indicates that the RAS addresses have been latched in the primary memory, and b) the end of cycle restore pulse 24.

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Incrementer With Row-To-Column Address Strobe Carry-In Capability

This incrementer circuit allows the chip's full word length address inputs to be incremented by one without external hardware or software requirements. The circuit allows the high-order carry-out of the row address strobe (RAS) to be the low-order carry-in of the column address strobe (CAS) incrementation. Systems requiring such an operation, benefit in performance by using this incrementer circuit. As shown in the diagram, the incrementer 32 uses two flip-flop circuits. Depletion loads are shown, but any type of load device can be substituted. Two timing pulses from the primary memory chip 20 are required: a) a RAS true/complement (T/C) latching pulse 22 which indicates that the RAS addresses have been latched in the primary memory, and b) the end of cycle restore pulse
24. Both of these timing pulses are available from field-effect transistor (FET) dynamic random-access memories (DRAMs). The upper flip-flop circuit, comprised of transistors 1 through 7, latches the high-order carry-out 26 of the RAS address incrementation when the primary memory latches the incremental RAS addresses. Transistor 6 unconditionally pulls node B low and node A high. If the RAS address incrementation high order carry-out 26 is high, then 5 and 7 discharge node A and charge node B. This flip-flop node B output then becomes the low-order carry-in for the CAS address incrementation. The bottom flip-flop, comprised of tra...