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Two-Device Nondestructive Read-Out Cell With Stacked Metal Oxide Semiconductor Devices

IP.com Disclosure Number: IPCOM000060167D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Landler, PF: AUTHOR

Abstract

This article describes a stacked metal-oxide-semiconductor (MOS) dynamic cell structure featuring a nondestructive read-out (NDRO) capability. The cell may be formed in dense layout. Stacked MOS structures are proposed to achieve dense layouts of the basic two-device cell shown in Fig. 1. The concept consists of storing the information as an electrical charge on the gate of an NMOS sense device T1 using a PMOS write device T2 and a write enable line W/W. This allows for non-destructive DC read out. Referring to Fig. 2, information is written into a selected wordline by bringing both the word line W/R and the write line W/W to VH and providing the data on the bit line B/L as a zero or VH potential. This charges capacitor C1 (node G) either negatively (-VH + VTP) or to zero with respect to W/R.

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Two-Device Nondestructive Read-Out Cell With Stacked Metal Oxide Semiconductor Devices

This article describes a stacked metal-oxide-semiconductor (MOS) dynamic cell structure featuring a nondestructive read-out (NDRO) capability. The cell may be formed in dense layout. Stacked MOS structures are proposed to achieve dense layouts of the basic two-device cell shown in Fig. 1. The concept consists of storing the information as an electrical charge on the gate of an NMOS sense device T1 using a PMOS write device T2 and a write enable line W/W. This allows for non-destructive DC read out. Referring to Fig. 2, information is written into a selected wordline by bringing both the word line W/R and the write line W/W to VH and providing the data on the bit line B/L as a zero or VH potential. This charges capacitor C1 (node G) either negatively (-VH + VTP) or to zero with respect to W/R. This charge can be sensed nondestructively during the read cycle by having the bit sense line B/L floating at zero while the bit read line is raised to VH.An alternate implementation is to use an NMOS device for T2 and a PMOS device for T1 and change the operating potential accordingly. A typical cell layout is shown in Fig. 3. T1 is formed by the standard recessed oxide self- aligned gate process in an n-type substrate (doped for p-channel enhancement mode operation) using an oxide/nitride gate. After Poly 1 oxidation, Poly 2 is lightly doped with boron for n-channel enhancement operation...