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CMOS Transfer Gate Exclusive or Circuit

IP.com Disclosure Number: IPCOM000060170D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Runyon, SL: AUTHOR

Abstract

The circuit shown in Fig. 1 offers fewer devices than most existing CMOS XOR circuits, resulting in circuit density advantages. It also has better performance. This circuit, shown in Fig. 1, implements the logical XOR function. Devices 4-7 provide the XOR function itself, and devices 2 and 3 provide high output drive capability and buffer the inputs from the output load. Device 1 provides positive feedback to ensure that device 2 is fully turned off when both inputs are 1. Without this device, a high level on both inputs will produce a level on the internal node that is degraded by -VT, causing device 2 to remain partially conductive when it should be turned off, and resulting in DC power consumption as well as an uncertain output level.

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CMOS Transfer Gate Exclusive or Circuit

The circuit shown in Fig. 1 offers fewer devices than most existing CMOS XOR circuits, resulting in circuit density advantages. It also has better performance. This circuit, shown in Fig. 1, implements the logical XOR function. Devices 4-7 provide the XOR function itself, and devices 2 and 3 provide high output drive capability and buffer the inputs from the output load. Device 1 provides positive feedback to ensure that device 2 is fully turned off when both inputs are 1. Without this device, a high level on both inputs will produce a level on the internal node that is degraded by -VT, causing device 2 to remain partially conductive when it should be turned off, and resulting in DC power consumption as well as an uncertain output level. With device 1 added, once the output begins to switch, device 1 will start to conduct, and will raise the voltage of the internal node above the VDD-VT voltage necessary to ensure that device 2 turns completely off. This will also turn devices 6 and 7 off, isolating the internal node from the inputs and preventing current flow through the input devices. This design eliminates DC current from flowing in the output state, thus eliminating DC power consumption and ensuring that the output level will be acceptable. This circuit also offers increased circuit density over other current "state-of-the-art" designs because it requires only 7 devices, whereas most other current CMOS designs use 10 tr...