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Analysis of RIE Damage

IP.com Disclosure Number: IPCOM000060173D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Chiu, TY: AUTHOR [+4]

Abstract

This article relates generally to integrated circuit fabrication and, more particularly, to a method of analyzing damage from reactive ion etching during silicon wafer processing. Improved reliability in the assessment of damage due to reactive ion etching results from the avoidance of processing steps subsequent to the etching. In-situ analytical evaluation is made by construction of a JFET-like device without auxiliary junction formation or treatment. The technique uses a conductive channel with source and drain electrodes, but with one gate electrode that is on the back of the substrate. The top gate area is replaced by bare silicon or insulators, such as silicon dioxide or silicon nitride.

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Analysis of RIE Damage

This article relates generally to integrated circuit fabrication and, more particularly, to a method of analyzing damage from reactive ion etching during silicon wafer processing. Improved reliability in the assessment of damage due to reactive ion etching results from the avoidance of processing steps subsequent to the etching. In-situ analytical evaluation is made by construction of a JFET- like device without auxiliary junction formation or treatment. The technique uses a conductive channel with source and drain electrodes, but with one gate electrode that is on the back of the substrate. The top gate area is replaced by bare silicon or insulators, such as silicon dioxide or silicon nitride. The top surface is exposed to reactive ion etching (RIE) which changes the surface potential because of damage to the silicon or to the inside of the insulator. This modulates channel conductance because of changes in depletion width or channel width. The gate voltage is then varied to maintain fixed channel conduction, and the variation is used to infer the extent of defect levels introduced in the forbidden gap or inside the insulator. An example of construction of a test device is shown in Figs. 1-3. In Fig. 1, silicon substrate 1 of p+ material with n type epitaxial layer 2 has an oxide 3 grown thereon and selectively protected via developed photoresist 4. After selective oxide removal with a boric hydrofluoric acid dip, phosphorous ion implantat...