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Browse Prior Art Database

System for Checking Data Processing System Control Circuit Malfunctions

IP.com Disclosure Number: IPCOM000060222D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Kienzle, TC: AUTHOR [+3]

Abstract

In data processing systems, one of the more difficult areas to check for proper operation is the control circuit. The checking system described herein performs this check by means of timing the start and end of system operations, such as "fetch", "store", etc., and also checks that the number of simultaneous operations does not exceed predetermined limits. The checking system described can be replicated, with each checking system being used to monitor a portion, or sub-system of the overall data processing system. As shown in the drawing, the checking control logic unit 1 contains priority control logic 2, operation start/end detection logic 3 and operation control logic 4. Operation input 5 connects to the priority control logic 2 and keeps unit 1 informed when operations are taking place.

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System for Checking Data Processing System Control Circuit Malfunctions

In data processing systems, one of the more difficult areas to check for proper operation is the control circuit. The checking system described herein performs this check by means of timing the start and end of system operations, such as "fetch", "store", etc., and also checks that the number of simultaneous operations does not exceed predetermined limits. The checking system described can be replicated, with each checking system being used to monitor a portion, or sub- system of the overall data processing system. As shown in the drawing, the checking control logic unit 1 contains priority control logic 2, operation start/end detection logic 3 and operation control logic 4. Operation input 5 connects to the priority control logic 2 and keeps unit 1 informed when operations are taking place. The operation control logic 4 of unit 1 may receive signals on cancel input 6 and also sends out busy signals 7. The operation start/end detection logic 3 provides an operation start signal 8 which resets the timing counter unit 9 to the zero count state. Counter unit 9 also receives system timing pulses 17 which makes the counter unit 9 increase its count. When the count reaches a predetermined value, the timing counter unit 9 produces end-count signal 15 which is connected to the time limit detector unit 13. The operation start signal 8 is also an input to the start/end register unit 10. The start/end register unit 10 acts as an up-down counter and increments up one count for each operation start signal 8 it receives. The start/end logic 3 provides a single-end signal 11 to register unit 10 when a single operation is completed within a particular data system cycle. Single-end signal 11 decrements start/end register unit 10 down by one count. In some conditions, it is possible for two operations being performed to be completed simultaneously. The st...