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Recovery From an Intermediate Microprocessor Operating State

IP.com Disclosure Number: IPCOM000060225D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Graves, SB: AUTHOR [+2]

Abstract

This article describes a technique that detects and corrects error conditions in a microprocessor. A standard approach to determine if a microprocessor is operating properly is to dedicate a processor port pin to the generation of "keep alive" pulses. These pulses are generated via software on a timely basis and are monitored via hardware. If the processor gets "lost" or stops functioning, the external circuitry senses this condition and generates a reset pulse to the processor. It has been observed after power line transient (PLT) noise that the processor can be in an indeterminant state such that it can execute code in the read-only store (ROS) but the stack addresses stored in the random access memory (RAM) are either destroyed or altered.

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Recovery From an Intermediate Microprocessor Operating State

This article describes a technique that detects and corrects error conditions in a microprocessor. A standard approach to determine if a microprocessor is operating properly is to dedicate a processor port pin to the generation of "keep alive" pulses. These pulses are generated via software on a timely basis and are monitored via hardware. If the processor gets "lost" or stops functioning, the external circuitry senses this condition and generates a reset pulse to the processor. It has been observed after power line transient (PLT) noise that the processor can be in an indeterminant state such that it can execute code in the read-only store (ROS) but the stack addresses stored in the random access memory (RAM) are either destroyed or altered. Since the "keep alive" pulses are generated by code in the ROS, the pulses continue to be generated even though other parts of the processor are not functioning properly. Therefore, no reset pulse is generated. To correct this problem, a specific location in the RAM is used as an indicator of whether the data in the RAM was altered or destroyed due to PLT types of noise. After the processor is reset, a unique data byte is placed in the RAM. Now, before each "keep alive" pulse is generated, this byte in the RAM is checked and compared with a "hard coded" value in the ROS. If there is a difference, it is apparent that the RAM has been altered. In such a case, the pro...